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Red Hat Bugzilla – Attachment 638771 Details for
Bug 873388
[abrt] xorg-x11-server-Xorg-1.12.3-2.fc17: Xorg server crashed
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File: Xorg.0.log
Xorg.0.log (text/plain), 4.30 MB, created by
Фукидид
on 2012-11-05 18:05:39 UTC
(
hide
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Description:
File: Xorg.0.log
Filename:
MIME Type:
Creator:
Фукидид
Created:
2012-11-05 18:05:39 UTC
Size:
4.30 MB
patch
obsolete
>[ 30.138] >X.Org X Server 1.12.3 >Release Date: 2012-07-09 >[ 30.138] X Protocol Version 11, Revision 0 >[ 30.138] Build Operating System: 2.6.32-220.17.1.el6.x86_64 >[ 30.138] Current Operating System: Linux localhost.localdomain 3.6.3-1.fc17.x86_64 #1 SMP Mon Oct 22 15:32:35 UTC 2012 x86_64 >[ 30.138] Kernel command line: BOOT_IMAGE=/vmlinuz-3.6.3-1.fc17.x86_64 root=/dev/mapper/vg-lv_root ro rd.md=0 rd.dm=0 SYSFONT=latarcyrheb-sun16 rd.luks.uuid=luks-ef07a2a5-552e-4e98-b486-b459a86b8290 KEYTABLE=ru rd.lvm.lv=vg/lv_root rd.lvm.lv=vg/lv_swap LANG=ru_RU.UTF-8 rhgb quiet >[ 30.138] Build Date: 20 September 2012 07:51:23AM >[ 30.138] Build ID: xorg-x11-server 1.12.3-2.fc17 >[ 30.138] Current version of pixman: 0.24.4 >[ 30.138] Before reporting problems, check http://wiki.x.org > to make sure that you have the latest version. >[ 30.138] Markers: (--) probed, (**) from config file, (==) default setting, > (++) from command line, (!!) notice, (II) informational, > (WW) warning, (EE) error, (NI) not implemented, (??) unknown. >[ 30.138] (==) Log file: "/var/log/Xorg.0.log", Time: Mon Nov 5 18:18:49 2012 >[ 30.139] (==) Using config directory: "/etc/X11/xorg.conf.d" >[ 30.139] (==) Using system config directory "/usr/share/X11/xorg.conf.d" >[ 30.139] (==) No Layout section. Using the first Screen section. >[ 30.139] (==) No screen section available. Using defaults. >[ 30.139] (**) |-->Screen "Default Screen Section" (0) >[ 30.139] (**) | |-->Monitor "<default monitor>" >[ 30.139] (==) No monitor specified for screen "Default Screen Section". > Using a default monitor configuration. >[ 30.139] (==) Automatically adding devices >[ 30.139] (==) Automatically enabling devices >[ 30.139] (==) FontPath set to: > catalogue:/etc/X11/fontpath.d, > built-ins >[ 30.139] (==) ModulePath set to "/usr/lib64/xorg/modules" >[ 30.139] (II) The server relies on udev to provide the list of input devices. > If no devices become available, reconfigure udev or disable AutoAddDevices. >[ 30.139] (II) Loader magic: 0x7c6ac0 >[ 30.140] (II) Module ABI versions: >[ 30.140] X.Org ANSI C Emulation: 0.4 >[ 30.140] X.Org Video Driver: 12.0 >[ 30.140] X.Org XInput driver : 16.0 >[ 30.140] X.Org Server Extension : 6.0 >[ 30.140] (--) PCI:*(0:1:5:0) 1002:9616:1002:0000 rev 0, Mem @ 0xd0000000/268435456, 0xfeaf0000/65536, 0xfe900000/1048576, I/O @ 0x0000d000/256, BIOS @ 0x????????/131072 >[ 30.141] (II) LoadModule: "extmod" >[ 30.141] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so >[ 30.141] (II) Module extmod: vendor="X.Org Foundation" >[ 30.141] compiled for 1.12.3, module version = 1.0.0 >[ 30.141] Module class: X.Org Server Extension >[ 30.141] ABI class: X.Org Server Extension, version 6.0 >[ 30.141] (II) Loading extension SELinux >[ 30.141] (II) Loading extension MIT-SCREEN-SAVER >[ 30.141] (II) Loading extension XFree86-VidModeExtension >[ 30.141] (II) Loading extension XFree86-DGA >[ 30.141] (II) Loading extension DPMS >[ 30.141] (II) Loading extension XVideo >[ 30.141] (II) Loading extension XVideo-MotionCompensation >[ 30.141] (II) Loading extension X-Resource >[ 30.141] (II) LoadModule: "dbe" >[ 30.142] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so >[ 30.142] (II) Module dbe: vendor="X.Org Foundation" >[ 30.142] compiled for 1.12.3, module version = 1.0.0 >[ 30.142] Module class: X.Org Server Extension >[ 30.142] ABI class: X.Org Server Extension, version 6.0 >[ 30.142] (II) Loading extension DOUBLE-BUFFER >[ 30.142] (II) LoadModule: "glx" >[ 30.142] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so >[ 30.142] (II) Module glx: vendor="X.Org Foundation" >[ 30.142] compiled for 1.12.3, module version = 1.0.0 >[ 30.142] ABI class: X.Org Server Extension, version 6.0 >[ 30.142] (==) AIGLX enabled >[ 30.142] (II) Loading extension GLX >[ 30.142] (II) LoadModule: "record" >[ 30.142] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so >[ 30.143] (II) Module record: vendor="X.Org Foundation" >[ 30.143] compiled for 1.12.3, module version = 1.13.0 >[ 30.143] Module class: X.Org Server Extension >[ 30.143] ABI class: X.Org Server Extension, version 6.0 >[ 30.143] (II) Loading extension RECORD >[ 30.143] (II) LoadModule: "dri" >[ 30.143] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so >[ 30.143] (II) Module dri: vendor="X.Org Foundation" >[ 30.143] compiled for 1.12.3, module version = 1.0.0 >[ 30.143] ABI class: X.Org Server Extension, version 6.0 >[ 30.143] (II) Loading extension XFree86-DRI >[ 30.143] (II) LoadModule: "dri2" >[ 30.143] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so >[ 30.143] (II) Module dri2: vendor="X.Org Foundation" >[ 30.143] compiled for 1.12.3, module version = 1.2.0 >[ 30.143] ABI class: X.Org Server Extension, version 6.0 >[ 30.144] (II) Loading extension DRI2 >[ 30.144] (==) Matched ati as autoconfigured driver 0 >[ 30.144] (==) Matched vesa as autoconfigured driver 1 >[ 30.144] (==) Matched modesetting as autoconfigured driver 2 >[ 30.144] (==) Matched fbdev as autoconfigured driver 3 >[ 30.144] (==) Assigned the driver to the xf86ConfigLayout >[ 30.144] (II) LoadModule: "ati" >[ 30.144] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so >[ 30.144] (II) Module ati: vendor="X.Org Foundation" >[ 30.144] compiled for 1.12.0, module version = 6.14.99 >[ 30.144] Module class: X.Org Video Driver >[ 30.144] ABI class: X.Org Video Driver, version 12.0 >[ 30.144] (II) LoadModule: "radeon" >[ 30.144] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so >[ 30.145] (II) Module radeon: vendor="X.Org Foundation" >[ 30.145] compiled for 1.12.0, module version = 6.14.99 >[ 30.145] Module class: X.Org Video Driver >[ 30.145] ABI class: X.Org Video Driver, version 12.0 >[ 30.145] (II) LoadModule: "vesa" >[ 30.145] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so >[ 30.145] (II) Module vesa: vendor="X.Org Foundation" >[ 30.145] compiled for 1.12.0, module version = 2.3.1 >[ 30.145] Module class: X.Org Video Driver >[ 30.145] ABI class: X.Org Video Driver, version 12.0 >[ 30.145] (II) LoadModule: "modesetting" >[ 30.145] (WW) Warning, couldn't open module modesetting >[ 30.145] (II) UnloadModule: "modesetting" >[ 30.145] (II) Unloading modesetting >[ 30.145] (EE) Failed to load module "modesetting" (module does not exist, 0) >[ 30.145] (II) LoadModule: "fbdev" >[ 30.145] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so >[ 30.145] (II) Module fbdev: vendor="X.Org Foundation" >[ 30.145] compiled for 1.11.99.901, module version = 0.4.2 >[ 30.145] ABI class: X.Org Video Driver, version 12.0 >[ 30.145] (II) RADEON: Driver for ATI Radeon chipsets: > ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI), > ATI Radeon Mobility X300 (M24) 3152 (PCIE), > ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI), > ATI Radeon X600 (RV380) 3E50 (PCIE), > ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136, > ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP), > ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), > ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP), > ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), > ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP), > ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), > ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650, > ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237, > ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336, > ATI Radeon IGP330M/340M/350M (U2) 4337, > ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI), > ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP), > ATI Radeon X800PRO (R420) JI (AGP), > ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP), > ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP), > ATI Radeon Mobility 9800 (M18) JN (AGP), > ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP), > ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP), > ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP), > ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP), > ATI Radeon Mobility M7 LW (AGP), > ATI Mobility FireGL 7800 M7 LX (AGP), > ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), > ATI FireGL Mobility 9000 (M9) Ld (AGP), > ATI Radeon Mobility 9000 (M9) Lf (AGP), > ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI, > ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), > ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP), > ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), > ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP), > ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP), > ATI Radeon Mobility 9600 (M10) NQ (AGP), > ATI Radeon Mobility 9600 (M11) NR (AGP), > ATI Radeon Mobility 9600 (M10) NS (AGP), > ATI FireGL Mobility T2 (M10) NT (AGP), > ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP), > ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), > ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), > ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI), > ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI), > ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI), > ATI Radeon Mobility X300 (M22) 5460 (PCIE), > ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE), > ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE), > ATI Radeon X800PRO (R423) UI (PCIE), > ATI Radeon X800LE (R423) UJ (PCIE), > ATI Radeon X800SE (R423) UK (PCIE), > ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE), > ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE), > ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE), > ATI FireGL unknown (R423) UR (PCIE), > ATI FireGL unknown (R423) UT (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility Radeon X700 XL (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834, > ATI Radeon Mobility 9100 IGP (U3) 5835, > ATI Radeon XPRESS 200 5954 (PCIE), > ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP), > ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), > ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI), > ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE), > ATI Radeon XPRESS 200M 5975 (PCIE), > ATI Radeon XPRESS 200 5A41 (PCIE), > ATI Radeon XPRESS 200M 5A42 (PCIE), > ATI Radeon XPRESS 200 5A61 (PCIE), > ATI Radeon XPRESS 200M 5A62 (PCIE), > ATI Radeon X300 (RV370) 5B60 (PCIE), > ATI Radeon X600 (RV370) 5B62 (PCIE), > ATI Radeon X550 (RV370) 5B63 (PCIE), > ATI FireGL V3100 (RV370) 5B64 (PCIE), > ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE), > ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), > ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), > ATI Mobility Radeon X800 XT (M28) (PCIE), > ATI Mobility FireGL V5100 (M28) (PCIE), > ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE), > ATI Radeon X850 XT PE (R480) (PCIE), > ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE), > ATI unknown Radeon / FireGL (R480) 5D50 (PCIE), > ATI Radeon X850 XT (R480) (PCIE), > ATI Radeon X800XT (R423) 5D57 (PCIE), > ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE), > ATI Radeon X700 PRO (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800, > ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800, > ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300, > ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800, > ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800, > ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505, > ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL, > ATI Mobility Radeon X1400, ATI Radeon X1300/X1550, > ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300, > ATI Mobility Radeon X1300, ATI Mobility Radeon X1300, > ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300, > ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350, > ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550, > ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450, > ATI Radeon X1300/X1550, ATI Mobility Radeon X2300, > ATI Mobility Radeon X2300, ATI Mobility Radeon X1350, > ATI Mobility Radeon X1350, ATI Mobility Radeon X1450, > ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350, > ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600, > ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600, > ATI Mobility FireGL V5200, ATI Mobility Radeon X1600, > ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600, > ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400, > ATI Mobility FireGL V5250, ATI Mobility Radeon X1700, > ATI Mobility Radeon X1700 XT, ATI FireGL V5200, > ATI Mobility Radeon X1700, ATI Radeon X2300HD, > ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300, > ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950, > ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560, > ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400, > ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560, > ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835, > ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200, > ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740, > ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT, > ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT, > ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600, > ATI Radeon 4800 Series, ATI Radeon HD 4870 x2, > ATI Radeon 4800 Series, ATI Radeon HD 4850 x2, > ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL), > ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2, > ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270, > AMD FireStream 9250, ATI FirePro V8700 (FireGL), > ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98, > ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series, > ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98, > ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP), > ATI Mobility Radeon HD 4670, ATI FirePro M5750, > ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP), > ATI RV730XT [Radeon HD 4670], ATI RADEON E4600, > ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650], > ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL), > ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830, > ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740, > ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770, > ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT, > ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000, > ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT, > ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610, > ATI FireMV 2260, ATI RV670, ATI Radeon HD3870, > ATI Mobility Radeon HD 3850, ATI Radeon HD3850, > ATI Mobility Radeon HD 3850 X2, ATI RV670, > ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2, > ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850, > ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550, > ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710, > ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series, > ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series, > ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630, > ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT, > ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP, > ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630, > ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600, > ATI FireGL V3600, ATI Radeon HD 2600 LE, > ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470, > ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series, > ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430, > ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450, > ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series, > ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO, > ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO, > ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670, > ATI Mobility FireGL V5700, ATI Mobility FireGL V5725, > ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics, > ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics, > ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics, > ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2, > SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200, > ATI Radeon 4100, ATI Mobility Radeon HD 4200, > ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250, > AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics, > AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics, > AMD Radeon HD 6300 Series Graphics, > AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370, > AMD Firestream 9350, ATI Radeon HD 5800 Series, > ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series, > ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series, > ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series, > ATI Mobility Radeon HD 5800 Series, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, > ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series, > ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series, > ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series, > ATI Mobility Radeon HD 5000 Series, > ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670, > ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD, > ATI Mobility Radeon HD 5000 Series, > ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics, > ATI Mobility Radeon Graphics, CEDAR, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR, > ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN, > CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, > AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN, > CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series, > BARTS, BARTS, Mobility Radeon HD 6000 Series, > Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS, > AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series, > AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, > CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA, > ARUBA, ARUBA, ARUBA, ARUBA >[ 30.157] (II) VESA: driver for VESA chipsets: vesa >[ 30.157] (II) FBDEV: driver for framebuffer: fbdev >[ 30.157] (++) using VT number 1 > >[ 30.161] (II) [KMS] Kernel modesetting enabled. >[ 30.161] (WW) Falling back to old probe method for vesa >[ 30.161] (WW) Falling back to old probe method for fbdev >[ 30.161] (II) Loading sub module "fbdevhw" >[ 30.161] (II) LoadModule: "fbdevhw" >[ 30.161] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so >[ 30.161] (II) Module fbdevhw: vendor="X.Org Foundation" >[ 30.161] compiled for 1.12.3, module version = 0.0.2 >[ 30.161] ABI class: X.Org Video Driver, version 12.0 >[ 30.161] (II) RADEON(0): RADEONPreInit_KMS >[ 30.161] (II) RADEON(0): Creating default Display subsection in Screen section > "Default Screen Section" for depth/fbbpp 24/32 >[ 30.161] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32 >[ 30.161] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) >[ 30.161] (==) RADEON(0): Default visual is TrueColor >[ 30.161] (==) RADEON(0): RGB weight 888 >[ 30.161] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC) >[ 30.161] (--) RADEON(0): Chipset: "ATI Radeon 3000 Graphics" (ChipID = 0x9616) >[ 30.161] (II) RADEON(0): PCI card detected >[ 30.161] drmOpenDevice: node name is /dev/dri/card0 >[ 30.161] drmOpenDevice: open result is 8, (OK) >[ 30.161] drmOpenByBusid: Searching for BusID pci:0000:01:05.0 >[ 30.161] drmOpenDevice: node name is /dev/dri/card0 >[ 30.161] drmOpenDevice: open result is 8, (OK) >[ 30.161] drmOpenByBusid: drmOpenMinor returns 8 >[ 30.161] drmOpenByBusid: drmGetBusid reports pci:0000:01:05.0 >[ 30.161] (II) Loading sub module "exa" >[ 30.161] (II) LoadModule: "exa" >[ 30.161] (II) Loading /usr/lib64/xorg/modules/libexa.so >[ 30.161] (II) Module exa: vendor="X.Org Foundation" >[ 30.161] compiled for 1.12.3, module version = 2.5.0 >[ 30.161] ABI class: X.Org Video Driver, version 12.0 >[ 30.161] (II) RADEON(0): KMS Color Tiling: enabled >[ 30.162] (II) RADEON(0): KMS Pageflipping: enabled >[ 30.162] (II) RADEON(0): SwapBuffers wait for vsync: enabled >[ 30.196] (II) RADEON(0): Output VGA-0 has no monitor section >[ 30.199] (II) RADEON(0): Output HDMI-0 has no monitor section >[ 30.234] (II) RADEON(0): EDID for output VGA-0 >[ 30.234] (II) RADEON(0): Manufacturer: GSM Model: 575f Serial#: 139045 >[ 30.234] (II) RADEON(0): Year: 2009 Week: 11 >[ 30.234] (II) RADEON(0): EDID Version: 1.3 >[ 30.234] (II) RADEON(0): Analog Display Input, Input Voltage Level: 0.700/0.700 V >[ 30.234] (II) RADEON(0): Sync: Separate SyncOnGreen >[ 30.234] (II) RADEON(0): Max Image Size [cm]: horiz.: 48 vert.: 27 >[ 30.234] (II) RADEON(0): Gamma: 2.20 >[ 30.234] (II) RADEON(0): DPMS capabilities: StandBy Suspend Off; RGB/Color Display >[ 30.234] (II) RADEON(0): First detailed timing is preferred mode >[ 30.234] (II) RADEON(0): redX: 0.646 redY: 0.334 greenX: 0.303 greenY: 0.616 >[ 30.234] (II) RADEON(0): blueX: 0.147 blueY: 0.067 whiteX: 0.313 whiteY: 0.329 >[ 30.234] (II) RADEON(0): Supported established timings: >[ 30.234] (II) RADEON(0): 720x400@70Hz >[ 30.234] (II) RADEON(0): 640x480@60Hz >[ 30.234] (II) RADEON(0): 640x480@75Hz >[ 30.234] (II) RADEON(0): 800x600@60Hz >[ 30.234] (II) RADEON(0): 800x600@75Hz >[ 30.234] (II) RADEON(0): 1024x768@60Hz >[ 30.234] (II) RADEON(0): 1024x768@75Hz >[ 30.234] (II) RADEON(0): 1280x1024@75Hz >[ 30.234] (II) RADEON(0): Manufacturer's mask: 0 >[ 30.234] (II) RADEON(0): Supported standard timings: >[ 30.234] (II) RADEON(0): #0: hsize: 1680 vsize 1050 refresh: 60 vid: 179 >[ 30.234] (II) RADEON(0): #1: hsize: 1280 vsize 1024 refresh: 60 vid: 32897 >[ 30.234] (II) RADEON(0): #2: hsize: 1280 vsize 1024 refresh: 75 vid: 36737 >[ 30.234] (II) RADEON(0): #3: hsize: 1152 vsize 864 refresh: 75 vid: 20337 >[ 30.234] (II) RADEON(0): Supported detailed timing: >[ 30.234] (II) RADEON(0): clock: 148.5 MHz Image Size: 477 x 268 mm >[ 30.234] (II) RADEON(0): h_active: 1920 h_sync: 2008 h_sync_end 2052 h_blank_end 2200 h_border: 0 >[ 30.234] (II) RADEON(0): v_active: 1080 v_sync: 1084 v_sync_end 1089 v_blanking: 1125 v_border: 0 >[ 30.234] (II) RADEON(0): Supported detailed timing: >[ 30.234] (II) RADEON(0): clock: 146.2 MHz Image Size: 477 x 268 mm >[ 30.234] (II) RADEON(0): h_active: 1680 h_sync: 1784 h_sync_end 1960 h_blank_end 2240 h_border: 0 >[ 30.234] (II) RADEON(0): v_active: 1050 v_sync: 1053 v_sync_end 1059 v_blanking: 1089 v_border: 0 >[ 30.234] (II) RADEON(0): Ranges: V min: 56 V max: 75 Hz, H min: 30 H max: 83 kHz, PixClock max 155 MHz >[ 30.234] (II) RADEON(0): Monitor name: W2230 >[ 30.234] (II) RADEON(0): EDID (in hex): >[ 30.234] (II) RADEON(0): 00ffffffffffff001e6d5f57251f0200 >[ 30.234] (II) RADEON(0): 0b1301036a301b78eaabd5a5554d9d25 >[ 30.234] (II) RADEON(0): 115054a54b00b3008180818f714f0101 >[ 30.234] (II) RADEON(0): 010101010101023a801871382d40582c >[ 30.234] (II) RADEON(0): 4500dd0c1100001a21399030621a2740 >[ 30.234] (II) RADEON(0): 68b03600dd0c1100001c000000fd0038 >[ 30.234] (II) RADEON(0): 4b1e530f000a202020202020000000fc >[ 30.234] (II) RADEON(0): 0057323233300a202020202020200096 >[ 30.234] (II) RADEON(0): EDID vendor "GSM", prod id 22367 >[ 30.234] (II) RADEON(0): Using EDID range info for horizontal sync >[ 30.234] (II) RADEON(0): Using EDID range info for vertical refresh >[ 30.234] (II) RADEON(0): Printing DDC gathered Modelines: >[ 30.234] (II) RADEON(0): Modeline "1920x1080"x0.0 148.50 1920 2008 2052 2200 1080 1084 1089 1125 +hsync -vsync (67.5 kHz eP) >[ 30.234] (II) RADEON(0): Modeline "1680x1050"x0.0 146.25 1680 1784 1960 2240 1050 1053 1059 1089 -hsync +vsync (65.3 kHz e) >[ 30.234] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 30.234] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 30.234] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 30.234] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 30.234] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 30.234] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 30.234] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 30.234] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 30.234] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e) >[ 30.234] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 30.234] (II) RADEON(0): Printing probed modes for output VGA-0 >[ 30.234] (II) RADEON(0): Modeline "1920x1080"x60.0 148.50 1920 2008 2052 2200 1080 1084 1089 1125 +hsync -vsync (67.5 kHz eP) >[ 30.235] (II) RADEON(0): Modeline "1680x1050"x60.0 146.25 1680 1784 1960 2240 1050 1053 1059 1089 -hsync +vsync (65.3 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1680x945"x60.0 131.48 1680 1784 1960 2240 945 946 949 978 -hsync +vsync (58.7 kHz) >[ 30.235] (II) RADEON(0): Modeline "1400x1050"x60.0 121.75 1400 1488 1632 1864 1050 1053 1057 1089 -hsync +vsync (65.3 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1600x900"x60.0 118.96 1600 1696 1864 2128 900 901 904 932 -hsync +vsync (55.9 kHz) >[ 30.235] (II) RADEON(0): Modeline "1280x1024"x75.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1280x1024"x60.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1440x900"x75.0 136.75 1440 1536 1688 1936 900 903 909 942 -hsync +vsync (70.6 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1440x900"x59.9 106.50 1440 1520 1672 1904 900 903 909 934 -hsync +vsync (55.9 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1280x960"x60.0 108.00 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync (60.0 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1366x768"x60.0 85.89 1366 1439 1583 1800 768 769 772 795 -hsync +vsync (47.7 kHz) >[ 30.235] (II) RADEON(0): Modeline "1360x768"x60.0 85.50 1360 1424 1536 1792 768 771 777 795 +hsync +vsync (47.7 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1280x800"x74.9 106.50 1280 1360 1488 1696 800 803 809 838 -hsync +vsync (62.8 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1280x800"x59.8 83.50 1280 1352 1480 1680 800 803 809 831 +hsync -vsync (49.7 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1152x864"x75.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1280x768"x74.9 102.25 1280 1360 1488 1696 768 771 778 805 +hsync -vsync (60.3 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1280x768"x59.9 79.50 1280 1344 1472 1664 768 771 778 798 -hsync +vsync (47.8 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1024x768"x75.1 78.80 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.1 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1024x768"x70.1 75.00 1024 1048 1184 1328 768 771 777 806 -hsync -vsync (56.5 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1024x768"x60.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 30.235] (II) RADEON(0): Modeline "1024x576"x60.0 46.97 1024 1064 1168 1312 576 577 580 597 -hsync +vsync (35.8 kHz) >[ 30.235] (II) RADEON(0): Modeline "800x600"x72.2 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (48.1 kHz e) >[ 30.235] (II) RADEON(0): Modeline "800x600"x75.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 30.235] (II) RADEON(0): Modeline "800x600"x60.3 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 30.235] (II) RADEON(0): Modeline "800x600"x56.2 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (35.2 kHz e) >[ 30.235] (II) RADEON(0): Modeline "848x480"x60.0 33.75 848 864 976 1088 480 486 494 517 +hsync +vsync (31.0 kHz e) >[ 30.235] (II) RADEON(0): Modeline "640x480"x72.8 31.50 640 664 704 832 480 489 492 520 -hsync -vsync (37.9 kHz e) >[ 30.235] (II) RADEON(0): Modeline "640x480"x75.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 30.235] (II) RADEON(0): Modeline "640x480"x60.0 25.20 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 30.235] (II) RADEON(0): Modeline "720x400"x70.1 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 30.237] (II) RADEON(0): EDID for output HDMI-0 >[ 30.237] (II) RADEON(0): Output VGA-0 connected >[ 30.237] (II) RADEON(0): Output HDMI-0 disconnected >[ 30.237] (II) RADEON(0): Using exact sizes for initial modes >[ 30.237] (II) RADEON(0): Output VGA-0 using initial mode 1920x1080 +0+0 >[ 30.237] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated. >[ 30.237] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:10000000 visible:f7d7000 >[ 30.237] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM >[ 30.237] (**) RADEON(0): Display dimensions: (480, 270) mm >[ 30.237] (**) RADEON(0): DPI set to (101, 101) >[ 30.237] (II) Loading sub module "fb" >[ 30.237] (II) LoadModule: "fb" >[ 30.237] (II) Loading /usr/lib64/xorg/modules/libfb.so >[ 30.237] (II) Module fb: vendor="X.Org Foundation" >[ 30.237] compiled for 1.12.3, module version = 1.0.0 >[ 30.237] ABI class: X.Org ANSI C Emulation, version 0.4 >[ 30.237] (II) Loading sub module "ramdac" >[ 30.237] (II) LoadModule: "ramdac" >[ 30.237] (II) Module "ramdac" already built-in >[ 30.237] (II) UnloadModule: "vesa" >[ 30.237] (II) Unloading vesa >[ 30.237] (II) UnloadModule: "fbdev" >[ 30.238] (II) Unloading fbdev >[ 30.238] (II) UnloadSubModule: "fbdevhw" >[ 30.238] (II) Unloading fbdevhw >[ 30.238] (--) Depth 24 pixmap format is 32 bpp >[ 30.238] (II) RADEON(0): [DRI2] Setup complete >[ 30.238] (II) RADEON(0): [DRI2] DRI driver: r600 >[ 30.238] (II) RADEON(0): [DRI2] VDPAU driver: r600 >[ 30.238] (II) RADEON(0): Front buffer size: 8100K >[ 30.238] (II) RADEON(0): VRAM usage limit set to 221119K >[ 30.238] (II) RADEON(0): Initializing backing store >[ 30.238] (==) RADEON(0): Backing store disabled >[ 30.238] (II) RADEON(0): Direct rendering enabled >[ 30.238] (II) RADEON(0): Initializing Acceleration >[ 30.238] (II) RADEON(0): Setting EXA maxPitchBytes >[ 30.238] (II) EXA(0): Driver allocated offscreen pixmaps >[ 30.238] (II) EXA(0): Driver registered support for the following operations: >[ 30.238] (II) Solid >[ 30.238] (II) Copy >[ 30.238] (II) Composite (RENDER acceleration) >[ 30.238] (II) UploadToScreen >[ 30.238] (II) DownloadFromScreen >[ 30.238] (II) RADEON(0): Acceleration enabled >[ 30.238] (II) RADEON(0): Initializing DPMS >[ 30.238] (==) RADEON(0): DPMS enabled >[ 30.238] (II) RADEON(0): Initializing Cursor >[ 30.238] (==) RADEON(0): Silken mouse enabled >[ 30.238] (II) RADEON(0): Initializing Xv >[ 30.238] (II) RADEON(0): Set up textured video >[ 30.238] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video. >[ 30.238] (II) RADEON(0): [XvMC] Extension initialized. >[ 30.238] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message. >[ 30.238] (II) RADEON(0): Initializing kms color map >[ 30.238] (II) RADEON(0): RADEONScreenInit finished >[ 30.238] (--) RandR disabled >[ 30.238] (II) Initializing built-in extension Generic Event Extension >[ 30.238] (II) Initializing built-in extension SHAPE >[ 30.238] (II) Initializing built-in extension MIT-SHM >[ 30.238] (II) Initializing built-in extension XInputExtension >[ 30.238] (II) Initializing built-in extension XTEST >[ 30.238] (II) Initializing built-in extension BIG-REQUESTS >[ 30.238] (II) Initializing built-in extension SYNC >[ 30.238] (II) Initializing built-in extension XKEYBOARD >[ 30.238] (II) Initializing built-in extension XC-MISC >[ 30.238] (II) Initializing built-in extension XINERAMA >[ 30.238] (II) Initializing built-in extension XFIXES >[ 30.238] (II) Initializing built-in extension RENDER >[ 30.238] (II) Initializing built-in extension RANDR >[ 30.239] (II) Initializing built-in extension COMPOSITE >[ 30.239] (II) Initializing built-in extension DAMAGE >[ 30.240] (II) SELinux: Disabled by boolean >[ 30.817] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer >[ 30.817] (II) AIGLX: enabled GLX_INTEL_swap_event >[ 30.818] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control >[ 30.818] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects >[ 30.819] (II) AIGLX: Loaded and initialized r600 >[ 30.819] (II) GLX: Initialized DRI2 GL provider for screen 0 >[ 30.823] (II) RADEON(0): Setting screen physical size to 508 x 285 >[ 30.868] (II) XKB: Reusing cached keymap >[ 30.871] (II) config/udev: Adding input device Power Button (/dev/input/event1) >[ 30.871] (**) Power Button: Applying InputClass "evdev keyboard catchall" >[ 30.871] (**) Power Button: Applying InputClass "system-setup-keyboard" >[ 30.871] (II) LoadModule: "evdev" >[ 30.871] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so >[ 30.871] (II) Module evdev: vendor="X.Org Foundation" >[ 30.871] compiled for 1.12.0, module version = 2.7.0 >[ 30.871] Module class: X.Org XInput Driver >[ 30.871] ABI class: X.Org XInput driver, version 16.0 >[ 30.871] (II) Using input driver 'evdev' for 'Power Button' >[ 30.871] Option "XkbRules" "evdev" >[ 30.871] Option "XkbModel" "pc105" >[ 30.871] Option "XkbLayout" "ru,us" >[ 30.871] Option "_source" "server/udev" >[ 30.871] Option "name" "Power Button" >[ 30.871] Option "path" "/dev/input/event1" >[ 30.871] Option "device" "/dev/input/event1" >[ 30.871] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1" >[ 30.871] Option "driver" "evdev" >[ 30.871] Option "XkbVariant" "" >[ 30.871] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 30.871] (**) Power Button: always reports core events >[ 30.871] (**) evdev: Power Button: Device: "/dev/input/event1" >[ 30.871] (--) evdev: Power Button: Vendor 0 Product 0x1 >[ 30.872] (--) evdev: Power Button: Found keys >[ 30.872] (II) evdev: Power Button: Configuring as keyboard >[ 30.872] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1" >[ 30.872] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6) >[ 30.872] (**) Option "xkb_rules" "evdev" >[ 30.872] (**) Option "xkb_model" "pc105" >[ 30.872] (**) Option "xkb_layout" "ru,us" >[ 30.872] (WW) Option "xkb_variant" requires an string value >[ 30.872] (WW) Option "XkbVariant" requires an string value >[ 30.872] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 30.911] (II) config/udev: Adding input device Power Button (/dev/input/event0) >[ 30.911] (**) Power Button: Applying InputClass "evdev keyboard catchall" >[ 30.911] (**) Power Button: Applying InputClass "system-setup-keyboard" >[ 30.911] (II) Using input driver 'evdev' for 'Power Button' >[ 30.911] Option "XkbRules" "evdev" >[ 30.911] Option "XkbModel" "pc105" >[ 30.911] Option "XkbLayout" "ru,us" >[ 30.911] Option "_source" "server/udev" >[ 30.911] Option "name" "Power Button" >[ 30.911] Option "path" "/dev/input/event0" >[ 30.911] Option "device" "/dev/input/event0" >[ 30.911] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0" >[ 30.911] Option "driver" "evdev" >[ 30.911] Option "XkbVariant" "" >[ 30.911] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 30.911] (**) Power Button: always reports core events >[ 30.911] (**) evdev: Power Button: Device: "/dev/input/event0" >[ 30.911] (--) evdev: Power Button: Vendor 0 Product 0x1 >[ 30.911] (--) evdev: Power Button: Found keys >[ 30.911] (II) evdev: Power Button: Configuring as keyboard >[ 30.911] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0" >[ 30.912] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 7) >[ 30.912] (**) Option "xkb_rules" "evdev" >[ 30.912] (**) Option "xkb_model" "pc105" >[ 30.912] (**) Option "xkb_layout" "ru,us" >[ 30.912] (WW) Option "xkb_variant" requires an string value >[ 30.912] (WW) Option "XkbVariant" requires an string value >[ 30.912] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 30.912] (II) XKB: Reusing cached keymap >[ 30.913] (II) config/udev: Adding input device USB2.0 Camera (/dev/input/event4) >[ 30.913] (**) USB2.0 Camera: Applying InputClass "evdev keyboard catchall" >[ 30.913] (**) USB2.0 Camera: Applying InputClass "system-setup-keyboard" >[ 30.913] (II) Using input driver 'evdev' for 'USB2.0 Camera' >[ 30.913] Option "XkbRules" "evdev" >[ 30.913] Option "XkbModel" "pc105" >[ 30.913] Option "XkbLayout" "ru,us" >[ 30.913] Option "_source" "server/udev" >[ 30.913] Option "name" "USB2.0 Camera" >[ 30.913] Option "path" "/dev/input/event4" >[ 30.913] Option "device" "/dev/input/event4" >[ 30.913] Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.2/usb1/1-6/1-6:1.0/input/input4/event4" >[ 30.913] Option "driver" "evdev" >[ 30.913] Option "XkbVariant" "" >[ 30.913] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 30.914] (**) USB2.0 Camera: always reports core events >[ 30.914] (**) evdev: USB2.0 Camera: Device: "/dev/input/event4" >[ 30.914] (--) evdev: USB2.0 Camera: Vendor 0x1e4e Product 0x102 >[ 30.914] (--) evdev: USB2.0 Camera: Found keys >[ 30.914] (II) evdev: USB2.0 Camera: Configuring as keyboard >[ 30.914] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.2/usb1/1-6/1-6:1.0/input/input4/event4" >[ 30.914] (II) XINPUT: Adding extended input device "USB2.0 Camera" (type: KEYBOARD, id 8) >[ 30.914] (**) Option "xkb_rules" "evdev" >[ 30.914] (**) Option "xkb_model" "pc105" >[ 30.914] (**) Option "xkb_layout" "ru,us" >[ 30.914] (WW) Option "xkb_variant" requires an string value >[ 30.914] (WW) Option "XkbVariant" requires an string value >[ 30.914] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 30.914] (II) XKB: Reusing cached keymap >[ 30.915] (II) config/udev: Adding input device HDA ATI SB Line Out CLFE (/dev/input/event10) >[ 30.915] (II) No input driver specified, ignoring this device. >[ 30.915] (II) This device may have been added with another device file. >[ 30.916] (II) config/udev: Adding input device HDA ATI SB Line Out Surround (/dev/input/event11) >[ 30.916] (II) No input driver specified, ignoring this device. >[ 30.916] (II) This device may have been added with another device file. >[ 30.917] (II) config/udev: Adding input device HDA ATI SB Line Out Front (/dev/input/event12) >[ 30.917] (II) No input driver specified, ignoring this device. >[ 30.917] (II) This device may have been added with another device file. >[ 30.917] (II) config/udev: Adding input device HDA ATI SB Line (/dev/input/event5) >[ 30.917] (II) No input driver specified, ignoring this device. >[ 30.917] (II) This device may have been added with another device file. >[ 30.918] (II) config/udev: Adding input device HDA ATI SB Front Mic (/dev/input/event6) >[ 30.918] (II) No input driver specified, ignoring this device. >[ 30.918] (II) This device may have been added with another device file. >[ 30.919] (II) config/udev: Adding input device HDA ATI SB Rear Mic (/dev/input/event7) >[ 30.919] (II) No input driver specified, ignoring this device. >[ 30.919] (II) This device may have been added with another device file. >[ 30.919] (II) config/udev: Adding input device HDA ATI SB Front Headphone (/dev/input/event8) >[ 30.919] (II) No input driver specified, ignoring this device. >[ 30.919] (II) This device may have been added with another device file. >[ 30.920] (II) config/udev: Adding input device HDA ATI SB Line Out Side (/dev/input/event9) >[ 30.920] (II) No input driver specified, ignoring this device. >[ 30.920] (II) This device may have been added with another device file. >[ 30.921] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event2) >[ 30.921] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall" >[ 30.921] (**) AT Translated Set 2 keyboard: Applying InputClass "system-setup-keyboard" >[ 30.921] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard' >[ 30.921] Option "XkbRules" "evdev" >[ 30.921] Option "XkbModel" "pc105" >[ 30.921] Option "XkbLayout" "ru,us" >[ 30.921] Option "_source" "server/udev" >[ 30.921] Option "name" "AT Translated Set 2 keyboard" >[ 30.921] Option "path" "/dev/input/event2" >[ 30.921] Option "device" "/dev/input/event2" >[ 30.921] Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input2/event2" >[ 30.921] Option "driver" "evdev" >[ 30.921] Option "XkbVariant" "" >[ 30.921] Option "XkbOptions" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 30.921] (**) AT Translated Set 2 keyboard: always reports core events >[ 30.921] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event2" >[ 30.921] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1 >[ 30.921] (--) evdev: AT Translated Set 2 keyboard: Found keys >[ 30.921] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard >[ 30.921] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input2/event2" >[ 30.921] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 9) >[ 30.921] (**) Option "xkb_rules" "evdev" >[ 30.921] (**) Option "xkb_model" "pc105" >[ 30.921] (**) Option "xkb_layout" "ru,us" >[ 30.921] (WW) Option "xkb_variant" requires an string value >[ 30.921] (WW) Option "XkbVariant" requires an string value >[ 30.921] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,grp:shifts_toggle,grp_led:scroll" >[ 30.921] (II) XKB: Reusing cached keymap >[ 30.923] (II) config/udev: Adding input device ImPS/2 Logitech Wheel Mouse (/dev/input/event3) >[ 30.923] (**) ImPS/2 Logitech Wheel Mouse: Applying InputClass "evdev pointer catchall" >[ 30.923] (II) Using input driver 'evdev' for 'ImPS/2 Logitech Wheel Mouse' >[ 30.923] Option "XkbRules" "evdev" >[ 30.923] Option "XkbModel" "evdev" >[ 30.923] Option "XkbLayout" "us" >[ 30.923] Option "_source" "server/udev" >[ 30.923] Option "name" "ImPS/2 Logitech Wheel Mouse" >[ 30.923] Option "path" "/dev/input/event3" >[ 30.923] Option "device" "/dev/input/event3" >[ 30.923] Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input3/event3" >[ 30.923] Option "driver" "evdev" >[ 30.923] (**) ImPS/2 Logitech Wheel Mouse: always reports core events >[ 30.923] (**) evdev: ImPS/2 Logitech Wheel Mouse: Device: "/dev/input/event3" >[ 30.923] (--) evdev: ImPS/2 Logitech Wheel Mouse: Vendor 0x2 Product 0x5 >[ 30.923] (--) evdev: ImPS/2 Logitech Wheel Mouse: Found 3 mouse buttons >[ 30.923] (--) evdev: ImPS/2 Logitech Wheel Mouse: Found scroll wheel(s) >[ 30.923] (--) evdev: ImPS/2 Logitech Wheel Mouse: Found relative axes >[ 30.923] (--) evdev: ImPS/2 Logitech Wheel Mouse: Found x and y relative axes >[ 30.923] (II) evdev: ImPS/2 Logitech Wheel Mouse: Configuring as mouse >[ 30.923] (II) evdev: ImPS/2 Logitech Wheel Mouse: Adding scrollwheel support >[ 30.923] (**) evdev: ImPS/2 Logitech Wheel Mouse: YAxisMapping: buttons 4 and 5 >[ 30.923] (**) evdev: ImPS/2 Logitech Wheel Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200 >[ 30.923] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input3/event3" >[ 30.923] (II) XINPUT: Adding extended input device "ImPS/2 Logitech Wheel Mouse" (type: MOUSE, id 10) >[ 30.923] (II) evdev: ImPS/2 Logitech Wheel Mouse: initialized for relative axes. >[ 30.923] (**) ImPS/2 Logitech Wheel Mouse: (accel) keeping acceleration scheme 1 >[ 30.923] (**) ImPS/2 Logitech Wheel Mouse: (accel) acceleration profile 0 >[ 30.923] (**) ImPS/2 Logitech Wheel Mouse: (accel) acceleration factor: 2.000 >[ 30.923] (**) ImPS/2 Logitech Wheel Mouse: (accel) acceleration threshold: 4 >[ 30.923] (II) config/udev: Adding input device ImPS/2 Logitech Wheel Mouse (/dev/input/mouse0) >[ 30.923] (II) No input driver specified, ignoring this device. >[ 30.923] (II) This device may have been added with another device file. >[ 30.927] (II) RADEON(0): RADEONSaveScreen(2) >[ 30.962] (II) RADEON(0): EDID vendor "GSM", prod id 22367 >[ 30.962] (II) RADEON(0): Using hsync ranges from config file >[ 30.962] (II) RADEON(0): Using vrefresh ranges from config file >[ 30.962] (II) RADEON(0): Printing DDC gathered Modelines: >[ 30.962] (II) RADEON(0): Modeline "1920x1080"x0.0 148.50 1920 2008 2052 2200 1080 1084 1089 1125 +hsync -vsync (67.5 kHz eP) >[ 30.962] (II) RADEON(0): Modeline "1680x1050"x0.0 146.25 1680 1784 1960 2240 1050 1053 1059 1089 -hsync +vsync (65.3 kHz e) >[ 30.962] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 30.962] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 30.962] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 30.962] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 30.962] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 30.963] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 30.963] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 30.963] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 30.963] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e) >[ 30.963] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 32.114] (II) RADEON(0): EDID vendor "GSM", prod id 22367 >[ 32.114] (II) RADEON(0): Using hsync ranges from config file >[ 32.114] (II) RADEON(0): Using vrefresh ranges from config file >[ 32.114] (II) RADEON(0): Printing DDC gathered Modelines: >[ 32.114] (II) RADEON(0): Modeline "1920x1080"x0.0 148.50 1920 2008 2052 2200 1080 1084 1089 1125 +hsync -vsync (67.5 kHz eP) >[ 32.114] (II) RADEON(0): Modeline "1680x1050"x0.0 146.25 1680 1784 1960 2240 1050 1053 1059 1089 -hsync +vsync (65.3 kHz e) >[ 32.114] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 32.114] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 32.114] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 32.114] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 32.114] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 32.114] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 32.114] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 32.114] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 32.114] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e) >[ 32.114] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 43.386] (II) RADEON(0): EDID vendor "GSM", prod id 22367 >[ 43.386] (II) RADEON(0): Using hsync ranges from config file >[ 43.386] (II) RADEON(0): Using vrefresh ranges from config file >[ 43.386] (II) RADEON(0): Printing DDC gathered Modelines: >[ 43.386] (II) RADEON(0): Modeline "1920x1080"x0.0 148.50 1920 2008 2052 2200 1080 1084 1089 1125 +hsync -vsync (67.5 kHz eP) >[ 43.386] (II) RADEON(0): Modeline "1680x1050"x0.0 146.25 1680 1784 1960 2240 1050 1053 1059 1089 -hsync +vsync (65.3 kHz e) >[ 43.386] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 43.386] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 43.386] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 43.386] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 43.386] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 43.386] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 43.386] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 43.386] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 43.386] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e) >[ 43.386] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 43.419] (II) RADEON(0): EDID vendor "GSM", prod id 22367 >[ 43.419] (II) RADEON(0): Using hsync ranges from config file >[ 43.419] (II) RADEON(0): Using vrefresh ranges from config file >[ 43.419] (II) RADEON(0): Printing DDC gathered Modelines: >[ 43.419] (II) RADEON(0): Modeline "1920x1080"x0.0 148.50 1920 2008 2052 2200 1080 1084 1089 1125 +hsync -vsync (67.5 kHz eP) >[ 43.419] (II) RADEON(0): Modeline "1680x1050"x0.0 146.25 1680 1784 1960 2240 1050 1053 1059 1089 -hsync +vsync (65.3 kHz e) >[ 43.419] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 43.419] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 43.420] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 43.420] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 43.420] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 43.420] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 43.420] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 43.420] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 43.420] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e) >[ 43.420] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 43.426] (II) RADEON(0): RADEONSaveScreen(2) >[ 44.452] (II) RADEON(0): EDID vendor "GSM", prod id 22367 >[ 44.452] (II) RADEON(0): Using hsync ranges from config file >[ 44.452] (II) RADEON(0): Using vrefresh ranges from config file >[ 44.452] (II) RADEON(0): Printing DDC gathered Modelines: >[ 44.452] (II) RADEON(0): Modeline "1920x1080"x0.0 148.50 1920 2008 2052 2200 1080 1084 1089 1125 +hsync -vsync (67.5 kHz eP) >[ 44.452] (II) RADEON(0): Modeline "1680x1050"x0.0 146.25 1680 1784 1960 2240 1050 1053 1059 1089 -hsync +vsync (65.3 kHz e) >[ 44.452] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 44.452] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 44.452] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 44.452] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 44.452] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 44.452] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 44.452] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 44.452] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 44.452] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e) >[ 44.452] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 4865.877] (II) RADEON(0): RADEONSaveScreen(2) >[ 4865.877] (II) RADEON(0): RADEONSaveScreen(0) >[ 5219.711] (II) RADEON(0): RADEONSaveScreen(1) >[ 5472.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5472.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5472.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5472.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5472.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5472.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5472.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5472.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5472.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5472.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5472.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458d320] >[ 5472.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458d320] width 1920 pitch 7680 (/4 1920) >[ 5472.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2d40] >[ 5472.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2d40] width 1920 pitch 7680 (/4 1920) >[ 5472.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5472.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5472.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2d40] >[ 5472.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2d40] width 1920 pitch 7680 (/4 1920) >[ 5472.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5472.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5472.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2d40] >[ 5472.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2d40] width 1920 pitch 7680 (/4 1920) >[ 5472.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5472.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5472.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5472.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5472.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5472.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5472.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458d5a0] >[ 5472.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458d5a0] width 1920 pitch 7680 (/4 1920) >[ 5472.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5472.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5472.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5472.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5472.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458d5a0] >[ 5472.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458d5a0] width 1920 pitch 7680 (/4 1920) >[ 5473.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5473.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5473.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458d5a0] >[ 5473.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458d5a0] width 1920 pitch 7680 (/4 1920) >[ 5473.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5473.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5473.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458d5a0] >[ 5473.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458d5a0] width 1920 pitch 7680 (/4 1920) >[ 5473.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5473.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5473.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458d6e0] >[ 5473.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458d6e0] width 1920 pitch 7680 (/4 1920) >[ 5473.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5473.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5473.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5473.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5473.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5473.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5473.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5473.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5473.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5473.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5473.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5473.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5473.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5473.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5473.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5473.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5473.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5473.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5473.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5473.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5473.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458d960] >[ 5473.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458d960] width 1920 pitch 7680 (/4 1920) >[ 5473.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5473.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5473.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458da00] >[ 5473.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458da00] width 1920 pitch 7680 (/4 1920) >[ 5473.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5473.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5473.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458da00] >[ 5473.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458da00] width 1920 pitch 7680 (/4 1920) >[ 5473.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5473.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5473.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458da00] >[ 5473.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458da00] width 1920 pitch 7680 (/4 1920) >[ 5473.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5473.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5473.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5473.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5473.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5473.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5473.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5473.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5474.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458dbe0] >[ 5474.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458dbe0] width 1920 pitch 7680 (/4 1920) >[ 5474.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5474.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5474.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458dbe0] >[ 5474.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458dbe0] width 1920 pitch 7680 (/4 1920) >[ 5474.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5474.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5474.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458dbe0] >[ 5474.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458dbe0] width 1920 pitch 7680 (/4 1920) >[ 5474.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5474.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5474.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458dbe0] >[ 5474.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458dbe0] width 1920 pitch 7680 (/4 1920) >[ 5474.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5474.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5474.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458dbe0] >[ 5474.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458dbe0] width 1920 pitch 7680 (/4 1920) >[ 5474.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5474.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5474.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5474.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5474.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5474.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5474.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5474.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5474.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5474.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5474.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5474.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5474.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5474.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5474.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5474.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5474.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5474.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5474.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5474.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5474.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5474.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5474.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5474.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5474.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5474.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5474.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5474.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5474.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5474.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5474.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5474.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5474.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5474.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5474.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5474.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5475.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5475.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5475.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5475.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5475.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5475.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5475.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5475.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5475.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5475.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5475.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5475.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5475.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5475.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5475.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5475.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5475.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5475.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5475.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5475.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5475.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5475.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5475.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5475.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5475.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5475.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5475.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5475.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5475.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5475.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5475.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5475.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5475.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5475.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5475.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5475.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5475.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5475.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5475.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5475.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5475.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5475.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5475.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5475.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5475.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5475.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5475.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5475.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5475.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458cc50] >[ 5475.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458cc50] width 1920 pitch 7680 (/4 1920) >[ 5475.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5475.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5475.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5475.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5476.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5476.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5476.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5476.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5476.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5476.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5476.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5476.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5476.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5476.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5476.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5476.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5476.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5476.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5476.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5476.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5476.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5476.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5476.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5476.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5476.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5476.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5476.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5476.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5476.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5476.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5476.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5476.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5476.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5476.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5476.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5476.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5476.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5476.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5476.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5476.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5476.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5476.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5476.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5476.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5476.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5476.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5476.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5476.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5476.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5476.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5476.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5476.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5476.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5476.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5476.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e620] >[ 5476.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e620] width 1920 pitch 7680 (/4 1920) >[ 5476.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5476.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5476.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5477.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5477.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5477.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5477.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5477.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5477.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5477.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5477.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5477.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5477.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5477.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5477.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5477.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5477.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5477.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5477.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5477.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5477.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5477.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5477.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5477.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5477.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5477.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5477.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5477.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5477.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5477.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5477.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5477.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5477.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5477.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5478.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5478.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5478.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5478.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5478.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5478.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5478.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5478.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5478.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5478.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5478.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5478.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5478.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5478.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5478.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5478.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5478.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5478.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5478.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5478.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5478.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5478.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5478.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5478.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5478.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5478.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5478.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5478.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5478.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5478.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5478.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5478.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5478.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5478.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5478.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5478.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5479.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5479.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5479.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5479.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5479.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5479.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5479.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5479.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5479.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5479.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5479.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5479.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5479.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5479.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5479.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5479.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5479.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5479.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5479.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5479.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5479.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5479.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5479.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5479.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5479.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5479.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5479.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5479.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5479.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5480.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5480.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5480.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5480.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5480.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5480.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5480.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5480.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5480.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5480.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5480.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5480.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5480.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5480.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5480.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5480.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5480.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5480.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5480.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5480.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5480.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5480.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5480.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5480.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5480.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5480.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5480.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5480.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5480.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5480.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5480.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5480.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5481.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5481.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5481.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5481.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5481.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5481.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5481.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5481.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5481.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5481.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5481.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5481.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5481.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5481.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5481.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5481.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5481.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5481.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5481.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5481.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5481.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5481.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5481.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5481.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5481.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5481.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5481.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5481.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5481.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5481.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5481.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5481.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5481.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5481.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5481.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5481.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5481.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5481.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5481.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5481.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5481.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5481.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5481.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5481.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5481.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5481.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5481.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5481.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5481.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5481.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5481.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5482.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5482.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5482.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5482.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5482.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5482.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5482.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5482.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5482.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5482.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5482.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5482.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5482.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5482.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5482.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5482.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5482.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5482.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5482.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5482.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5482.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5482.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5482.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5482.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5482.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5482.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5482.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5482.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5482.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5482.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5482.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5482.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5482.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5482.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5482.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5482.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5482.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5482.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5482.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5482.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5482.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5482.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5482.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5482.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5482.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5482.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5482.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5482.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5482.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5482.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5482.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5482.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5483.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5483.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5483.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5483.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5483.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5483.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5483.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5483.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5483.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5483.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5483.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5483.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5483.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5483.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5483.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5483.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5483.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5483.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5483.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5483.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5483.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5483.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5483.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5483.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5483.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5483.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5483.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5483.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5483.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5483.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5483.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5484.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5484.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5484.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5484.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5484.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5484.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5484.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5484.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5484.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5484.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5484.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5484.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5484.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5484.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5484.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5484.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5484.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5484.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5484.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5484.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5484.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5484.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5484.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5484.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5484.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5484.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5484.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5484.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5484.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5484.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5485.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5485.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5485.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5485.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5485.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5485.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5485.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5485.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5485.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5485.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5485.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5485.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5485.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5485.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5485.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5485.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5485.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5485.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5485.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5485.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5485.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5485.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5485.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5485.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5485.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5485.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5485.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5485.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5486.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5486.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5486.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5486.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5486.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5486.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5486.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5486.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5486.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5486.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5486.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5486.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5486.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5486.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5486.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5486.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5486.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5486.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5486.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5486.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5486.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5486.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5486.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5486.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5486.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5486.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5486.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5486.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5486.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5486.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5486.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5486.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5486.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5486.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5486.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5486.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5486.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5486.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5486.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5486.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5486.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5486.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5486.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5486.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5486.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5486.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5486.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5486.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5486.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5487.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5487.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5487.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5487.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5487.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5487.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5487.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5487.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5487.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5487.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5487.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5487.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5487.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5487.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5487.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5487.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5487.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5487.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5487.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5487.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5487.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5487.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5487.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5487.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5487.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5487.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5487.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5487.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5487.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5487.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5487.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5487.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5487.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5487.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5487.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5487.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5487.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5487.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5487.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5487.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5487.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5487.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5487.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5487.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5487.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5487.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5487.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5487.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5487.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5488.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5488.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5488.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5488.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5488.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5488.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5488.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5488.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5488.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5488.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5488.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5488.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5488.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5488.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5488.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5488.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5488.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5488.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5488.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5488.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5488.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5488.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5488.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5488.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5488.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5488.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5488.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5488.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5488.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5488.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5488.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5488.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5488.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5488.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5488.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5488.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5488.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5488.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5488.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5488.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5488.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5488.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5488.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5488.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5488.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5488.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5488.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5489.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5489.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5489.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5489.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5489.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5489.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5489.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5489.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5489.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5489.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5489.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5489.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5489.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5489.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5489.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5489.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5489.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5489.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5489.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5489.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5489.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5489.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5489.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5489.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5489.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5489.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5489.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5489.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5489.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5489.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5489.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5489.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5489.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5489.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5489.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5489.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5489.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5489.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5489.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5489.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5489.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5489.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5489.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5489.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5489.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5489.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5489.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5490.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5490.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5490.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5490.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5490.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5490.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5490.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5490.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5490.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5490.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5490.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5490.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5490.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5490.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5490.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5490.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5490.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5490.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5490.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5490.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5490.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5490.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5490.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5490.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5490.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5490.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5490.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5490.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5490.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5490.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5490.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5490.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5490.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5490.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5490.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5490.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5490.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5490.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5490.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5490.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5490.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5490.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5490.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5490.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5490.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5490.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5491.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5491.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5491.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5491.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5491.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5491.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5491.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5491.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5491.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5491.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5491.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5491.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5491.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5491.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5491.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5491.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5491.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5491.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5491.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5491.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5491.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5491.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5491.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5491.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5491.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5491.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5491.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5491.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5491.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5491.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5491.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5491.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5491.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5491.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5491.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5491.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5491.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5491.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5491.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5491.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5491.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5491.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5491.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5491.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5491.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5491.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5492.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5492.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5492.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5492.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5492.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5492.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5492.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5492.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5492.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5492.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5492.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5492.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5492.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5492.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5492.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5492.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5492.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5492.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5492.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5492.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5492.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5492.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5492.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5492.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5492.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5492.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5492.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5492.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5492.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5492.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5492.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5492.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5492.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5492.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5492.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5492.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5492.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5492.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5493.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5493.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5493.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5493.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5493.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5493.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5493.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5493.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5493.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5493.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5493.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5493.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5493.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5493.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5493.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5493.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5493.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5493.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5493.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5493.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5493.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5493.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5493.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5493.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5493.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5493.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5493.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5493.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5493.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5493.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5493.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5493.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5493.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5493.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5493.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5493.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5493.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5493.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5493.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5493.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5493.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5493.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5493.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5493.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5494.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5494.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5494.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5494.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5494.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5494.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5494.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458f010] >[ 5494.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458f010] width 1920 pitch 7680 (/4 1920) >[ 5494.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5494.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5494.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5494.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5494.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5494.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5494.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5494.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5494.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5494.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5494.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5494.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5494.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5494.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5494.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5494.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5494.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5494.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5494.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5494.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5494.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5494.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5494.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5494.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5494.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5494.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5494.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5494.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5494.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5494.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5494.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5494.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5494.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5494.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5494.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5494.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5495.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5495.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5495.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5495.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5495.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5495.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5495.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5495.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5495.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5495.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5495.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5495.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5495.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5495.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5495.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5495.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5495.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5495.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5495.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5495.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5495.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5495.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5495.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5495.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5495.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5495.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5495.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5495.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5495.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5495.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5495.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5495.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5495.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5495.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5495.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5495.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5495.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5495.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5495.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5495.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5495.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5495.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5495.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5495.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5496.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5496.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5496.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5496.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5496.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5496.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5496.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5496.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5496.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5496.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5496.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5496.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5496.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5496.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5496.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5496.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5496.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5496.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5496.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5496.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5496.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5496.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5496.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5496.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5496.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5496.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5496.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5496.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5496.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5496.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5496.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5496.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5496.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5496.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5496.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5496.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5496.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5496.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5496.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5496.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5496.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5496.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5497.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5497.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5497.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5497.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5498.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5498.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5498.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5498.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5498.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5498.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5498.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5498.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5498.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5498.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5498.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5498.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5498.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5498.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5498.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5498.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5498.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5498.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5498.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5498.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5498.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5498.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5498.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5498.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5498.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5498.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5498.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5498.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5498.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5498.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5498.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5498.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5498.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5498.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5498.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5498.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5498.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5498.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5498.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5498.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5498.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5499.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5499.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5499.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5499.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5499.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5499.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5499.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5499.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5499.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5499.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5499.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5499.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5499.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5499.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5499.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5499.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5499.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5499.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5499.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5499.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5499.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5499.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5499.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5499.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5499.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5499.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5499.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5499.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5499.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5499.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5499.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5499.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5499.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5499.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5499.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5499.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5499.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5499.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5499.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5499.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5500.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5500.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5500.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5500.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5500.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5500.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5500.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5500.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5500.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5500.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5500.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5500.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5500.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5500.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5500.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5500.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5500.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5500.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5500.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5500.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5500.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5500.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5500.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5500.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5500.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5500.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5500.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5500.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5500.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5500.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5500.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5500.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5500.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5500.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5500.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5500.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5500.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5500.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5500.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5500.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5500.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5500.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5501.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5501.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5501.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5501.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5501.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5501.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5501.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5501.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5501.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5501.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5501.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5501.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5501.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5501.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5501.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5501.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5501.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a0af0] >[ 5501.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a0af0] width 1920 pitch 7680 (/4 1920) >[ 5501.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5501.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5501.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a0af0] >[ 5501.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a0af0] width 1920 pitch 7680 (/4 1920) >[ 5501.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5501.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5501.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5501.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5501.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5501.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5501.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5501.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5501.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5501.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5501.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b450] >[ 5501.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b450] width 1920 pitch 7680 (/4 1920) >[ 5501.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5501.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5501.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b450] >[ 5501.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b450] width 1920 pitch 7680 (/4 1920) >[ 5501.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5501.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5502.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5502.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5502.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5502.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5502.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5502.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5502.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5502.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5502.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5502.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5502.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5502.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5502.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5502.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5502.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5502.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5502.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5502.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5502.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5502.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5502.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5502.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5502.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5502.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5502.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5502.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5502.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5502.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5502.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5502.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5502.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5502.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5502.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5502.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5502.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5502.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5502.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5502.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5503.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5503.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5503.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5503.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5503.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5503.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5503.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5503.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5503.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5503.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5503.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5503.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5503.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5503.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5503.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5503.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5503.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5503.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5503.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5503.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5503.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5503.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5503.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5503.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5503.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5503.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5503.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5503.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5503.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5503.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5503.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5503.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5503.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5503.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5503.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5503.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5503.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5503.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5503.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5503.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5504.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5504.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5504.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5504.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5504.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5504.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5504.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5504.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5504.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5504.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5504.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5504.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5504.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5504.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5504.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5504.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5504.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5504.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5504.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5504.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5504.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5504.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5504.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5504.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5504.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5504.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5504.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5504.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5504.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5504.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5504.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5504.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5504.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5504.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5504.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5504.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5504.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5504.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5504.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5504.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5505.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5505.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5505.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5505.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5505.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5505.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5505.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5505.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5505.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5505.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5505.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5505.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5505.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5505.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5505.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5505.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5505.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5505.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5505.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5505.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5505.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5505.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5505.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5505.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5505.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5505.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5505.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5505.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5505.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5505.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5505.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5505.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5505.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5505.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5505.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5505.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5505.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5505.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5505.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5506.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5506.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5506.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5506.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5506.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5506.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5506.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5506.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5506.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5506.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5506.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5506.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5506.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5506.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5506.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5506.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5506.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5506.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5506.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5506.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5506.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5506.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5506.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5507.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5507.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5507.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5507.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5508.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5508.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5508.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5508.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5508.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5508.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5508.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5508.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5508.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5508.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5508.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5508.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5508.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5508.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5508.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5508.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5508.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5508.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5508.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5508.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5508.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5508.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5508.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5508.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5508.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5508.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5508.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5508.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5508.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5508.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5508.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5508.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5508.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5508.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5508.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5508.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5508.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5508.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5509.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5509.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5509.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5509.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5509.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5509.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5509.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5509.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5509.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5509.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5509.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5509.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5509.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5509.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5509.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5509.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5509.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5509.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5509.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5509.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5509.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5509.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5509.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5509.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5509.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5509.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5509.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5509.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5509.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5509.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5509.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5509.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5509.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5509.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5509.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5509.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5509.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5509.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5510.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5510.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5510.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5510.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5510.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5510.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5510.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5510.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5510.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5510.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5510.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5510.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5510.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5510.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5510.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5510.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5510.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5510.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5510.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5510.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5510.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5510.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5510.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5510.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5510.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5510.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5510.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5510.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5510.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5510.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5510.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5510.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5510.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5510.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5510.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5510.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5510.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5510.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5510.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5510.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5511.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5511.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5511.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5511.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5511.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5511.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5511.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5511.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5511.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5511.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5511.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5511.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5511.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5511.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5511.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5511.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5511.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5511.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5511.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5511.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5511.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5511.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5511.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5511.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5511.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5511.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5511.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5511.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5511.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5511.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5511.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5511.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5511.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5511.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5511.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5511.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5511.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5511.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5512.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5512.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5512.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5512.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5512.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5512.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5512.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5512.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5512.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5512.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5512.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5512.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5512.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5512.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5512.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5512.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5512.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5512.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5512.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5512.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5512.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5512.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5512.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5512.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5512.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5512.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5512.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5512.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5512.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5512.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5512.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5512.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5512.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5512.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5512.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5512.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5512.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5512.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5512.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5512.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5513.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5513.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5513.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5513.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5513.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5513.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5513.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5513.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5513.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5513.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5513.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5513.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5513.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5513.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5513.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5513.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5513.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5513.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5513.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5513.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5513.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5513.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5513.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5513.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5513.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5513.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5513.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5513.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5513.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5513.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5513.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5513.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5513.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5513.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5513.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5513.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5513.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5513.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5513.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5513.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5514.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5514.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5514.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5514.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5514.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5514.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5514.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5514.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5514.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5514.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5514.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5514.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5514.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5514.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5514.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5514.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5514.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5514.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5514.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5514.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5514.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5514.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5514.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5514.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5514.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5514.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5514.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5514.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5514.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5514.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5514.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5514.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5514.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5514.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5514.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5514.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5514.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5514.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5514.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5515.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5515.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5515.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5515.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5515.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5515.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5515.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5515.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5515.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5515.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5515.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5515.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5515.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5515.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5515.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5515.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5515.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5515.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5515.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5515.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5515.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5515.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5515.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5515.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5515.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5515.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5515.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5515.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5515.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5515.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5515.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5515.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5515.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5515.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5515.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5515.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5515.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5515.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5515.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5516.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5516.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5516.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5516.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5516.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5516.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5516.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5516.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5516.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5516.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5516.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5516.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5516.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5516.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5516.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5516.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5516.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5516.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5516.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5516.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5516.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5516.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5516.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5516.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5516.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5516.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5516.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5516.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5516.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5516.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5516.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5516.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5516.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5516.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5516.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5516.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5516.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5516.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5516.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5516.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5517.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5517.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5517.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5517.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5517.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5517.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5517.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5517.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5517.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5517.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5517.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5517.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5517.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5517.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5517.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5517.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5517.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5517.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5517.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5517.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5517.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5517.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5517.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5517.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5517.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5517.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5517.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5517.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5517.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5517.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5517.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5517.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5517.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5517.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5517.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5517.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5517.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5517.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5517.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5518.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5518.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5518.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5518.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5518.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5518.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5518.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5518.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5518.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5518.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5518.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5518.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5518.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5518.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5518.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5518.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5518.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5518.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5518.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5518.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5518.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5518.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5518.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5518.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5518.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5518.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5518.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5518.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5518.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5518.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5518.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5518.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5518.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5518.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5518.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5518.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5518.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5518.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5518.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5519.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5519.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5519.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5519.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5519.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5519.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5519.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5519.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5519.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5519.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5519.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5519.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5519.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5519.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5519.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5519.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5519.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5519.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5519.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5519.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5519.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5519.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5519.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5519.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5519.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5519.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5519.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5519.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5519.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5519.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5519.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5519.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5519.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5519.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5519.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5519.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5519.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5519.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5520.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5520.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5520.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5520.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5520.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5520.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5520.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5520.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5520.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5520.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5520.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5520.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5520.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5520.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5520.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5520.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5520.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5520.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5520.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5520.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5520.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5520.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5520.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5520.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5520.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5520.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5520.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5520.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5520.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5520.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5520.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5520.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5520.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5520.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5520.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5520.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5520.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5520.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5521.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5521.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5521.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5521.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5521.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5521.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5521.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5521.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5521.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5521.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5521.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5521.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5521.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5521.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5521.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5521.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5521.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5521.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5521.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5521.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5521.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5521.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5521.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5521.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5521.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5521.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5521.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5521.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5521.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5521.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5521.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5521.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5521.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5521.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5521.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5521.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5521.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5521.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5522.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5522.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5522.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5522.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5522.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5522.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5522.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5522.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5522.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5522.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5522.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5522.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5522.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5522.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5522.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5522.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5522.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5522.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5522.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5522.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5522.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5522.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5522.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5522.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5522.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5522.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5522.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5522.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5522.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5522.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5522.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5522.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5522.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5522.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5522.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5522.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5522.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5523.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5523.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5523.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5523.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5523.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5523.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5523.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5523.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5523.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5523.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5523.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5523.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5523.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5523.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5523.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5523.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5523.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5523.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5523.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5523.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5523.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5523.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5523.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5523.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5523.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5523.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5523.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5523.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5523.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5523.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5523.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5523.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5523.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5523.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5523.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5523.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5524.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5524.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5524.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5524.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5524.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5524.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5524.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5524.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5524.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5524.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5524.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5524.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5524.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5524.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5524.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5524.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5524.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5524.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5524.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5524.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5524.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5524.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5524.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5524.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5524.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5524.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5524.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5524.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5524.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5524.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5524.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5524.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5524.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5524.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5524.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5524.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5524.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5525.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5525.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5525.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5525.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5525.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5525.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5525.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5525.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5525.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5525.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5525.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5525.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5525.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5525.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5525.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5525.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5525.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5525.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5525.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5525.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5525.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5525.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5525.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5525.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5525.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5525.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5525.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5525.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5525.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5525.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5525.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5525.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5525.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5525.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5525.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5525.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5525.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5525.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5526.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5526.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5526.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5526.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5526.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5526.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5526.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5526.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5526.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5526.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5526.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5526.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5526.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5526.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5526.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5526.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5526.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5526.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5526.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5526.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5526.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5526.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5526.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5526.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5526.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5526.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5526.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5526.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5526.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5526.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5526.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5526.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5526.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5526.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5526.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5526.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5527.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5527.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5527.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5527.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5527.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5527.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5527.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5527.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5527.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5527.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5527.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5527.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5527.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5527.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5527.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5527.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5527.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5527.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5527.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5527.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5527.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5527.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5527.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5527.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5527.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5527.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5527.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5527.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5527.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5527.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5527.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5527.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5527.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5527.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5527.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5527.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5528.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5528.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5528.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5528.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5528.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5528.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5528.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5528.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5528.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5528.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5528.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5528.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5528.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5528.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5528.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5528.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5528.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5528.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5528.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5528.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5528.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5528.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5528.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5528.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5528.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5528.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5528.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5528.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5528.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5528.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5528.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5528.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5528.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5528.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5528.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5528.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5528.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5529.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5529.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5529.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5529.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5529.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5529.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5529.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5529.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5529.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5529.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5529.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5529.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5529.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5529.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5529.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5529.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5529.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5529.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5529.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5529.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5529.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5529.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5529.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5529.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5529.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5529.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5529.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5529.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5529.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5529.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5529.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5529.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5529.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5529.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5529.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5529.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5529.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5530.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5530.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5530.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5530.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5530.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5530.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5530.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5530.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5530.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5530.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5530.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5530.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5530.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5530.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5530.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5530.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5530.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5530.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5530.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5530.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5530.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5530.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5530.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5530.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5530.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5530.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5530.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5530.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5530.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5530.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5530.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5530.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5531.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5531.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5531.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5531.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5531.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5531.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5531.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5531.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5531.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5531.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5531.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5531.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5531.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5531.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5531.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5531.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5531.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5531.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5531.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5531.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5531.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5531.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5531.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5531.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5531.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5531.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5531.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5531.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5531.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5531.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5531.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5531.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5531.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5531.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5531.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5531.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5531.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5531.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5532.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5532.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5532.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5532.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5532.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5532.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5532.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5532.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5532.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5532.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5532.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5532.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5532.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5532.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5532.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5532.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5532.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5533.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5533.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5533.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5533.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5533.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5533.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5533.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5533.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5533.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5533.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5533.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5533.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5533.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5533.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5533.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5533.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5533.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5533.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5533.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5533.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5533.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5533.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5533.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5533.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5533.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5533.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5533.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5533.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5533.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5533.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5533.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5533.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5533.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5533.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5533.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5533.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5533.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5534.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5534.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5534.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5534.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5534.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5534.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5534.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5534.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5534.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5534.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5534.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5534.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5534.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5534.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5534.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5534.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5534.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5534.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5534.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5534.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5534.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5534.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5534.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5534.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5534.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5534.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5534.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5534.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5534.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5534.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5534.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5534.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5534.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5535.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5535.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5535.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5535.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5535.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5535.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5535.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5535.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5535.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5535.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5535.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5535.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5535.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5535.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5535.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5535.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5535.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5535.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5535.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5535.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5535.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5536.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5536.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5536.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5536.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5536.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5536.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5536.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5536.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5536.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5536.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5536.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5536.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5536.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5536.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5536.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5536.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5536.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5536.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5536.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5536.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5536.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5536.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5536.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5536.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5536.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5536.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5536.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5536.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5536.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5536.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5536.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5536.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5537.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5537.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5537.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5537.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5537.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5537.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5537.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5537.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5537.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5537.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5537.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5537.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5537.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5537.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5537.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5537.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5537.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5537.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5537.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5537.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5537.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5537.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5537.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5537.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5537.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5537.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5537.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5537.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5537.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5537.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5537.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5537.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5537.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5537.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5538.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5538.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5538.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5538.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5539.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5539.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5539.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5539.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5540.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5540.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5540.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5540.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5540.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5540.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5540.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5540.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5540.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5540.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5540.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5540.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5540.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5540.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5540.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5540.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5540.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5540.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5540.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5540.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5540.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5540.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5540.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5540.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5540.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5540.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5540.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5540.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5540.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5540.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5540.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5540.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5540.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5540.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5540.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5540.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5540.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5540.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5540.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5540.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5540.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5540.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5540.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5540.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5540.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5540.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5540.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5540.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5540.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5540.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5540.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5540.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5540.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5540.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5541.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5541.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5541.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5541.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5541.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5541.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5541.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5541.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5541.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5541.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5541.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5541.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5541.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5542.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5542.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5542.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5542.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5542.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5542.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5542.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5542.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5542.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5542.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5542.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5542.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5542.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5542.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5542.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5542.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5542.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5542.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5542.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5542.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5542.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5542.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5542.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5542.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5542.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5542.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5542.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5543.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5543.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5543.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5543.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5543.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5543.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5543.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5543.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5543.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5543.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5543.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5543.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5543.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5543.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5543.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5543.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5543.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5543.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5543.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5543.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5543.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5543.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5543.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5543.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5543.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5543.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5543.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5543.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5544.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5544.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5544.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5544.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5544.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5544.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5544.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5544.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5544.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5545.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5545.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5545.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5545.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5545.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5545.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5545.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5545.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5545.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5545.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5545.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5545.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5546.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5546.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5546.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5546.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5546.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5546.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5546.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5546.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5546.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5546.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5546.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5546.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5546.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5546.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5546.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5546.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5546.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5546.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5546.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5546.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5546.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5546.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5546.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5546.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5546.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5546.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5546.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5546.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5546.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5546.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5546.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5546.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5546.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5546.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5546.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5546.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5546.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5546.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5546.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5546.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5546.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5546.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5547.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5547.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5547.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5547.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5547.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5547.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5547.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5547.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5547.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5547.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5547.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5547.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5547.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5547.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5547.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5547.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5547.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5547.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5547.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5547.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5547.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5547.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5547.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5548.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5548.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5548.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5548.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5548.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5548.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5548.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5548.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5548.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5548.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5548.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5548.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5548.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5548.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5548.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5548.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5548.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5548.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5548.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5548.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5548.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5548.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5548.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5548.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5548.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5548.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5548.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5548.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5548.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5548.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5548.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5548.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5549.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5549.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5549.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5549.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5549.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5549.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5549.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5549.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5549.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5549.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5549.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5549.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5549.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5549.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5549.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5549.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5549.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5549.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5549.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5549.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5549.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5549.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5549.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5549.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5549.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5549.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5549.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5549.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5549.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5549.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5549.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5549.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5549.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5549.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5549.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5549.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5549.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5549.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5549.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5549.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5549.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5549.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5549.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5549.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5549.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5549.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5549.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5550.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5550.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5550.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5550.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5550.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5550.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5550.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5550.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5550.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5550.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5550.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5551.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5551.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5551.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5551.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5551.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5551.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5551.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5551.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5551.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5551.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5551.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5551.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5551.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5551.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5551.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5551.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5551.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5551.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5551.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5551.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5551.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5551.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5551.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5551.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5551.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5551.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5551.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5551.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5551.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5551.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5551.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5551.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5551.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5551.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5551.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5551.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5551.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5551.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5551.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5551.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5551.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5551.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5551.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5551.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5551.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5551.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5552.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5552.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5552.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5552.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5552.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5552.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5552.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5552.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5552.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5552.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5552.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5552.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5552.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5552.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5552.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5552.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5552.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5552.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5552.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5552.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5552.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5552.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5552.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5552.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5552.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5552.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5552.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5552.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5553.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5553.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5553.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5553.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5553.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5553.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5553.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5553.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5553.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5553.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5553.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5553.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5553.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5553.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5553.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5553.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5553.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5553.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5553.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5553.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5553.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5553.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5553.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5553.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5553.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5553.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5553.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5553.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5554.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5554.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5554.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5554.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5554.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5554.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5554.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5554.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5554.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5554.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5554.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5554.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5554.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5554.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5554.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5554.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5554.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5554.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5554.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5554.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5554.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5554.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5554.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5554.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5554.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5554.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5554.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5554.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5554.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5554.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5554.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5554.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5554.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5554.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5554.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5554.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5554.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5554.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5554.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5554.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5554.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5554.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5554.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5555.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5555.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5555.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5555.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5555.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5555.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5555.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5555.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5555.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5555.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5555.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5555.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5555.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5555.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5555.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5555.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5555.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5555.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5555.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5555.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5555.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5555.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5555.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5555.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5555.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5555.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5555.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5555.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5555.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5555.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5555.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5555.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5555.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5555.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5555.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5555.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5555.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5555.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5555.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5555.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5555.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5555.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5555.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5556.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5556.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5556.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5556.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5556.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5556.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5556.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5556.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5556.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5556.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5556.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5556.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5556.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5556.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5556.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5556.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5556.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5556.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5556.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5556.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5556.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5556.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5556.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5556.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5556.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5556.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5556.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5556.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5556.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5556.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5556.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5556.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5556.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5556.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5556.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5556.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5556.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5556.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5556.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5556.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5556.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5556.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5556.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5557.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5557.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5557.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5557.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5557.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5557.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5557.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5557.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5557.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5557.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5557.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5557.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5557.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5557.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5557.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5557.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5557.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5557.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5557.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5557.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5557.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5557.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5557.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5557.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5557.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5557.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5557.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5557.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5558.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5558.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5558.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5558.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5558.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5558.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5558.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5558.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5558.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5558.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5558.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5558.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5558.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5558.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5558.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5558.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5558.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5558.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5558.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5558.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5558.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5558.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5558.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5558.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5558.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5558.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5558.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5558.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5558.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5558.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5558.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5558.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5558.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5558.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5558.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5558.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5558.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5558.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5558.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5558.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5558.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5558.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5558.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5559.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5559.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5559.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5559.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5559.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5559.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5559.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5559.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5559.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5559.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5559.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5559.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5559.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5559.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5559.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5559.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5559.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5559.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5559.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5559.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5559.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5559.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5559.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5559.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5559.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5559.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5559.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5559.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5559.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5559.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5559.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5559.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5559.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5559.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5559.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5559.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5559.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5559.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5559.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5559.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5559.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5559.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5559.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5559.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5560.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5560.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5560.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5560.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5560.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5560.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5560.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5560.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5560.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5560.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5560.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5560.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5560.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5560.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5560.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5560.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5560.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5560.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5560.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5560.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5560.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5560.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5560.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5560.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5560.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5560.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5560.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5560.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5560.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5560.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5560.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5560.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5560.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5560.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5560.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5560.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5560.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5560.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5560.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5560.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5560.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5560.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5560.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5560.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5561.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5561.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5561.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5561.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5561.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5561.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5561.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5561.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5561.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5561.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5561.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5561.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5561.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5561.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5561.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5561.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5561.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5561.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5561.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5561.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5561.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5561.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5561.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5561.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5561.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5561.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5561.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5561.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5561.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5561.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5561.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5561.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5561.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5561.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5561.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5561.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5561.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5561.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5561.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5561.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5561.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5561.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5562.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5562.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5562.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5562.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5562.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5562.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5562.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5562.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5562.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5562.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5562.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5562.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5562.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5562.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5562.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5562.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5562.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5562.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5562.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5562.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5562.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5562.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5562.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5562.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5562.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5562.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5562.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5562.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5562.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5562.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5562.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5562.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5562.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5562.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5562.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5562.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5562.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5562.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5562.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5562.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5562.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5562.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5562.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5563.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5563.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5563.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5563.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5563.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5563.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5563.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5563.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5563.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5563.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5563.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5563.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5563.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5563.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5563.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5563.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5563.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5563.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5563.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5563.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5563.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5563.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5563.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5563.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5563.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5563.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5563.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5563.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5563.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5563.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5563.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5563.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5563.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5563.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5563.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5563.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5563.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5563.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5563.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5563.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5563.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5563.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5564.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5564.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5564.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5564.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5564.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5564.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5564.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5564.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5564.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5564.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5564.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5564.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5564.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5564.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5564.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5564.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5564.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5564.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5564.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5564.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5564.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5564.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5564.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5564.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5564.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5564.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5564.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5564.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5564.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5564.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5564.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5564.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5564.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5564.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5564.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5564.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5564.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5564.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5564.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5564.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5564.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5564.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5564.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5565.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5565.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5565.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5565.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5565.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5565.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5565.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5565.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5565.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5565.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5565.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5565.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5565.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5565.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5565.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5565.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5565.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5565.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5565.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5565.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5565.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5565.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5565.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5565.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5565.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5565.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5565.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5565.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5565.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5565.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5565.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5565.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5565.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5565.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5565.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5565.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5565.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5565.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5565.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5565.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5565.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5565.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5566.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5566.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5566.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5566.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5566.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5566.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5566.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5566.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5566.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5566.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5566.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5566.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5566.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5566.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5566.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5566.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5566.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5566.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5566.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5566.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5566.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5566.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5566.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5566.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5566.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5566.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5566.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5566.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5566.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5566.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5566.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5566.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5566.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5566.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5566.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5566.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5566.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5566.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5566.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5566.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5566.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5566.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5566.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5567.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5567.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5567.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5567.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5567.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5567.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5567.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5567.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5567.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5567.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5567.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5567.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5567.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5567.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5567.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5567.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5567.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5567.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5567.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5567.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5567.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5567.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5567.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5567.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5567.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5567.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5567.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5567.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5567.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5567.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5567.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5567.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5567.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5567.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5567.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5567.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5567.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5567.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5567.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5567.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5567.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5567.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5567.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5567.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5568.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5568.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5568.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5568.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5568.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5568.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5568.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5568.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5568.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5568.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5568.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5568.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5568.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5568.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5568.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5568.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5568.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5568.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5568.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5568.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5568.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5568.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5568.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5568.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5568.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5568.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5569.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5569.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5569.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5569.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5569.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5569.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5569.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5569.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5569.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5569.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5569.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5569.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5569.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5569.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5569.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5569.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5569.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5569.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5569.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5569.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5569.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5569.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5569.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5569.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5569.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5569.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5569.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5569.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5569.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5569.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5569.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5569.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5569.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5569.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5569.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5569.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5569.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5569.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5569.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5569.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5569.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5569.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5569.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5570.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5570.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5570.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5570.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5570.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5570.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5570.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5570.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5570.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5570.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5570.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5570.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5570.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5570.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5570.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5570.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5570.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5570.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5570.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5570.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5570.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5570.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5570.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5570.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5570.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5570.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5570.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5570.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5571.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5571.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5571.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5571.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5571.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5571.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5571.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5571.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5571.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5571.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5571.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5571.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5571.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5571.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5571.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5571.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5571.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5571.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5571.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5571.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5571.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5571.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5571.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5571.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5571.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5571.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5572.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5572.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5572.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5572.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5572.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5572.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5572.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5572.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5572.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5572.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5572.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5572.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5572.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5572.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5572.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5572.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5572.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5572.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5572.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5572.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5572.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5572.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5572.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5572.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5572.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5572.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5572.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5572.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5572.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5572.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5572.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5572.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5572.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5572.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5572.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5572.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5572.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5572.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5572.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5572.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5572.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5572.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5572.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5572.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5573.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5573.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5573.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5573.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5573.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5573.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5573.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5573.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5573.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5573.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5573.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5573.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5573.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5573.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5573.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5573.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5573.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5573.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5573.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5573.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5573.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5573.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5573.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5573.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5573.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5573.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5573.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5573.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5574.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5574.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5574.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5574.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5574.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5574.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5574.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5574.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5574.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5574.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5574.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5574.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5574.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5574.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5574.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5574.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5574.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5574.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5574.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5574.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5574.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5574.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5574.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5574.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5574.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5574.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5574.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5574.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5574.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5574.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5574.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5574.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5574.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5574.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5574.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5575.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5575.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5575.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5575.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5575.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5575.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5575.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5575.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5575.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5575.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5575.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5575.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5575.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5575.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5575.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5575.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5575.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5575.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5575.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5575.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5575.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5575.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5575.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5575.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5576.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5576.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5576.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5576.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5576.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5576.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5576.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5576.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5576.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5576.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5576.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5576.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5576.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5576.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5576.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5576.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5576.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5576.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5576.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5576.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5576.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5576.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5576.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5576.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5576.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5576.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5576.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5576.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5576.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5576.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5576.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5576.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5576.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5576.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5576.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5576.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5576.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5576.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5576.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5576.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5576.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5576.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5576.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5576.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5577.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5577.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5577.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5577.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5577.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5577.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5577.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5577.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5577.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5577.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5577.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5577.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5577.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5577.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5577.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5577.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5577.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5577.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5577.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5577.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5577.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5577.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5577.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5577.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5577.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5577.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5577.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5577.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5577.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5577.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5577.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5577.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5577.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5577.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5578.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5578.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5578.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5578.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5578.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5578.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5578.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5578.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5578.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5578.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5578.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5578.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5578.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5578.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5578.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5578.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5578.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5578.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5578.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5578.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5578.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5578.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5578.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5578.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5578.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5578.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5578.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5578.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5579.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5579.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5579.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5579.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5579.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5579.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5579.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5579.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5579.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5579.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5579.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5579.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5579.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5579.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5579.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5579.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5579.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5579.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5579.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5579.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5579.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5579.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5579.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5579.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5579.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5580.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5580.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5580.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5580.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5580.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5580.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5580.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5580.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5580.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5580.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5580.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5580.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5580.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5580.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5580.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5580.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5580.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5580.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5580.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5580.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5580.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5580.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5580.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5580.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5580.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5580.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5580.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5580.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5580.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5580.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5580.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5580.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5580.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5580.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5580.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5580.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5580.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5580.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5580.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5580.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5580.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5581.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5581.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5581.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5581.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5581.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5581.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5581.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5581.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5581.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5581.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5581.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5581.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5581.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5581.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5581.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5581.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5581.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5581.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5581.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5581.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5581.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5581.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5581.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5581.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5581.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5581.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5581.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5581.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5581.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5581.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5581.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5581.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5581.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5581.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5581.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5581.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5581.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5581.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5581.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5581.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5581.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5582.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5582.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5582.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5582.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5582.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5582.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5582.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5582.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5582.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5582.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5582.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5582.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5582.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5582.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5582.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5582.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5582.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5582.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5582.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5582.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5582.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5582.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5582.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5582.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5582.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5583.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5583.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5583.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5583.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5583.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5583.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5583.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5583.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5583.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5583.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5583.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5583.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5583.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5583.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5583.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5583.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5583.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5583.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5583.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5583.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5583.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5583.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5583.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5583.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5583.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5583.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5583.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5583.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5583.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5583.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5583.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5583.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5583.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5583.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5584.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5584.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5584.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5584.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5584.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5584.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5584.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5584.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5584.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5584.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5584.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f6d0] >[ 5584.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f6d0] width 1920 pitch 7680 (/4 1920) >[ 5584.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5584.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5584.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5584.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5584.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5584.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5584.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5584.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5584.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5584.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5584.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5584.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5584.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5584.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5584.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5584.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5584.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5584.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5584.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5584.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5584.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5584.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5584.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5584.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5584.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5584.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5584.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5584.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5584.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5585.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5585.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5585.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5585.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5585.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5585.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5585.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5585.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5585.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5585.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5585.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5585.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5585.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5585.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5585.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5585.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5585.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5585.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5585.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5585.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5585.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5585.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5585.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5585.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5585.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5586.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5586.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5586.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5586.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5586.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5586.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5586.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5586.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5586.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5586.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5586.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5586.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5586.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5586.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5586.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5586.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5586.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5586.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5586.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5586.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5586.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5586.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5586.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5586.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5586.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5586.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5586.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5586.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5586.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5586.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5586.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5586.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5586.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5586.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5587.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5587.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5587.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5587.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5587.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5587.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5587.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5587.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5587.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5587.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5587.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5587.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5587.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5587.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5587.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5587.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5587.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5587.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5587.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5587.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5587.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5587.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5587.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5588.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5588.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5588.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5588.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5588.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5588.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5588.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5588.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5588.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5588.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5588.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5588.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5588.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5588.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5588.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5588.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5588.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5588.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5588.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5588.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5588.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5588.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5588.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5589.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5589.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5589.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5589.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5589.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5589.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5589.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5589.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5589.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5589.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5589.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5589.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5589.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5589.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5589.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5589.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5589.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5589.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5589.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5589.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5589.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5589.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5589.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5589.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5589.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5589.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5589.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5589.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5589.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5589.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5589.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5589.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5589.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5589.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5589.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5589.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5589.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5589.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5589.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5589.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5589.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5590.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5590.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5590.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5590.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5590.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5590.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5590.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5590.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5590.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5590.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5590.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5590.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5590.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5590.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5590.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5590.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5590.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5590.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5590.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5590.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5590.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5590.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5590.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5590.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5590.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5591.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5591.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5591.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5591.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5591.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5591.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5591.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5591.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5591.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5591.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5591.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5591.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5591.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5591.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5591.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5591.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5591.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5591.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5591.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5591.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5591.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5591.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5591.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5591.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5592.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5592.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5592.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5592.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5592.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5592.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5592.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5592.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5592.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5592.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5592.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5592.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5592.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5592.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5592.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5592.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5592.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5592.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5592.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5592.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5592.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5592.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5592.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5592.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5593.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5593.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5593.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5593.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5593.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5593.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5593.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5593.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5593.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5593.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5593.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5593.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5593.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5593.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5593.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5593.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5593.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5593.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5593.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5593.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5593.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5593.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5593.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5594.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5594.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5594.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5594.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5595.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5595.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5595.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5595.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5595.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5595.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5595.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5595.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5595.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5595.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5595.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5595.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5595.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5595.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5595.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5595.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5595.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5595.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5596.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5596.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5596.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5596.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5596.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5596.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5596.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5596.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5596.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5596.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5596.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f4780] >[ 5596.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f4780] width 1920 pitch 7680 (/4 1920) >[ 5596.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5596.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5596.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5596.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5596.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5596.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5596.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5596.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5596.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5596.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5596.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5596.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5596.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5596.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5596.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5596.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5596.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5596.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5596.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5596.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5596.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5596.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5596.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5596.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5596.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5596.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5596.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5596.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5596.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5596.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5597.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5597.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5597.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5597.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5597.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5597.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5597.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5597.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5597.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5597.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5597.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5597.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5597.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5597.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5597.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5597.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5597.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40520b0] >[ 5597.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40520b0] width 1920 pitch 7680 (/4 1920) >[ 5597.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5597.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5597.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5597.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5597.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5597.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5597.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5597.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5597.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5597.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5597.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5597.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5597.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860d0] >[ 5597.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860d0] width 1920 pitch 7680 (/4 1920) >[ 5597.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5597.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5597.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5597.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5597.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5597.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5597.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5597.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5597.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5597.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5598.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5598.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5598.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5598.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5598.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5598.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5598.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5598.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5598.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5598.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5598.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5598.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5598.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5598.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5598.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5598.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5598.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5598.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5598.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5598.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5598.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5598.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5598.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5598.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5598.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5598.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5598.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5598.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5598.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5598.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5598.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5598.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5599.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5599.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5599.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45873f0] >[ 5599.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45873f0] width 1920 pitch 7680 (/4 1920) >[ 5599.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5599.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5599.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5599.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5599.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5599.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5599.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5599.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5599.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5599.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5599.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5599.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5599.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5599.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5599.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5599.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5599.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5599.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5599.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5599.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5599.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5600.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5600.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x443d020] >[ 5600.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x443d020] width 1920 pitch 7680 (/4 1920) >[ 5600.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5600.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5600.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5600.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5600.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5600.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5600.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5600.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5600.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5600.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5600.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5600.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5600.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5600.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5600.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5600.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5600.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5600.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5600.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5600.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5600.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5600.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5600.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5600.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5600.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5600.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5600.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5600.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5600.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5600.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5600.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5600.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5600.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5600.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5600.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5600.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5600.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5600.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5601.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5601.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5601.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5601.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5601.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5601.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5601.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5601.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5601.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5601.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5601.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5601.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5601.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5601.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5601.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5601.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5601.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5601.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5601.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5601.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5601.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5601.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5601.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5601.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5601.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5601.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5601.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5601.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5601.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5601.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5601.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5601.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5601.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5601.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5601.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5601.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5601.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5601.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5601.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5601.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5601.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5601.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5602.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5602.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5602.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5602.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5602.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5602.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5602.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5602.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5602.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5602.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5602.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5602.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5602.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5602.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5602.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5602.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5602.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5602.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5602.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5602.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5602.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5602.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5602.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4196500] >[ 5602.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4196500] width 1920 pitch 7680 (/4 1920) >[ 5603.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5603.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5603.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5603.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5603.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5603.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5603.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5603.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5603.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5603.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5603.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5603.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5603.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5603.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5603.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5603.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5603.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5603.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5603.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5603.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5603.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5603.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5603.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5603.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5603.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5603.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5603.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5603.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5603.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5603.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5603.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5603.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5603.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5603.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5603.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5603.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5603.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5603.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5603.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5603.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5603.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5603.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5604.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5604.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5604.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5604.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5604.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5604.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5604.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5604.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5604.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5604.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5604.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5604.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5604.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5604.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5604.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5604.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5604.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5604.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5604.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5604.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5604.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5604.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5605.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5605.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5605.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5605.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5605.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5605.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5605.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5605.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5605.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5605.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5605.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5605.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5605.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5605.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5605.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5605.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5605.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5605.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5605.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5605.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5605.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5605.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5605.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5605.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5605.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5605.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5605.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5605.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5605.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5606.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5606.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5606.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5606.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5606.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5606.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5606.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5606.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5606.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5606.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5606.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5606.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5606.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5606.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5606.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5606.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5606.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5606.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5606.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5606.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5606.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5606.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5606.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5606.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5606.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5606.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5606.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5606.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5606.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5606.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5606.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5606.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5606.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5606.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5606.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5606.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5606.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5606.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5606.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5606.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5606.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5606.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5606.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5606.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5607.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5607.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5607.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5607.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5607.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5607.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5607.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5607.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5607.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5607.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5607.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5607.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5607.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5607.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5607.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5607.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5607.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5607.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5607.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5607.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5607.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5607.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5607.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5607.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5607.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5607.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5607.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5607.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5607.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5607.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5607.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5607.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5607.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5607.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5607.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5607.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5607.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5607.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5607.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5607.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5607.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5607.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5607.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5607.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5607.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5607.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5607.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5607.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5607.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5607.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5607.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5607.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5607.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5607.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5608.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5608.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5608.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5608.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5608.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5608.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5608.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5608.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5608.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5608.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5608.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5608.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5608.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5608.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5608.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5608.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5608.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5608.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5608.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5608.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5608.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5608.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5608.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5608.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5608.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5608.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5608.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5608.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5608.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5608.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5608.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5608.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5608.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5608.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5608.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5608.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5608.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5608.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5608.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5609.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5609.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5609.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5609.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5609.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5609.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5609.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5609.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5609.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5609.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5609.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5609.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5609.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5609.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5609.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5610.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5610.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5610.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5610.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5610.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5610.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5610.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5610.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5610.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5610.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5610.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407cac0] >[ 5610.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407cac0] width 1920 pitch 7680 (/4 1920) >[ 5610.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5610.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5610.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5610.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5610.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5610.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5611.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5611.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5611.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5611.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5611.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5611.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5611.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5611.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5611.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5611.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5611.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5611.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5611.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5611.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5611.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5611.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5611.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5611.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5611.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5611.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5611.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5611.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5611.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5611.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5611.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5611.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5611.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5611.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5611.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5611.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5611.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5611.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5611.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5611.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5611.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5611.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5611.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5611.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5611.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5611.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5611.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5611.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5611.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5611.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5611.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5611.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5611.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5611.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5611.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5611.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5611.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5611.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5611.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5611.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5612.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5612.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5612.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5612.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5612.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5612.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5612.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5612.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5612.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5612.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5612.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5612.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5612.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5612.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5612.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5612.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5612.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5612.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5612.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5612.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5612.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5612.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5612.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5612.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5612.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585210] >[ 5612.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585210] width 1920 pitch 7680 (/4 1920) >[ 5612.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5612.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5612.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5612.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5612.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5612.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5613.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5613.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5613.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5613.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5613.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5613.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5613.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5613.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5613.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5613.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5613.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5613.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5613.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5613.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5613.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5614.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbd380] >[ 5614.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbd380] width 1920 pitch 7680 (/4 1920) >[ 5614.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5614.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5614.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5614.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5614.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5614.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5614.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5614.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5614.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5614.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5614.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5615.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5615.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5615.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5615.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5615.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5615.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5615.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5615.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5615.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5615.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5615.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5615.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5615.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5615.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5615.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5615.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5615.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5615.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5615.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5615.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5615.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5615.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5615.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5615.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5615.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5615.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5615.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5615.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5616.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5616.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5616.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5616.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5616.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5616.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5616.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5616.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5616.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5616.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5616.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5616.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5616.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5616.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5616.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5616.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5616.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5616.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5616.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5616.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5616.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5616.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5616.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5616.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5616.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5616.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5617.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5617.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5617.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5617.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5617.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5617.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5617.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5617.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5617.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5617.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5617.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5617.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5617.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5617.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5617.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5617.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5617.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5617.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5617.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5617.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5617.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5617.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5617.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5617.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5617.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5617.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5618.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5618.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5618.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5618.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5618.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5618.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d2b0] >[ 5618.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d2b0] width 1920 pitch 7680 (/4 1920) >[ 5618.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5618.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5618.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5618.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5618.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5618.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5618.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5618.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5618.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5618.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5618.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5618.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5618.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5618.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5618.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5618.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5618.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5618.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5618.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5618.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5618.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5618.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5618.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5618.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5618.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581da0] >[ 5618.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581da0] width 1920 pitch 7680 (/4 1920) >[ 5618.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5618.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5618.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5618.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5618.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5618.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5618.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5618.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5618.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5618.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5618.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5618.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5618.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5618.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5618.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5618.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5618.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5619.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5619.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5619.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5619.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5619.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5619.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5619.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5619.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5619.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5619.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5619.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5619.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5619.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5619.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc16e0] >[ 5619.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc16e0] width 1920 pitch 7680 (/4 1920) >[ 5619.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5619.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5619.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5619.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5619.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5619.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5619.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5619.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5619.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5619.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5619.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5619.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5619.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5619.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5619.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5619.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5619.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5619.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5620.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5620.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5620.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5620.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5620.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5620.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5620.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5620.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5620.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5620.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5620.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5620.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5620.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5620.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5620.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5620.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5620.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5620.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5620.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5620.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5620.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5620.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5620.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5620.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5620.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5620.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5621.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5621.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5621.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587050] >[ 5621.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587050] width 1920 pitch 7680 (/4 1920) >[ 5621.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5621.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5621.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5621.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5622.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5622.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5622.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5622.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5622.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5622.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5622.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5622.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5622.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5622.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5622.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5622.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5622.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5622.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5622.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5622.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5622.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5622.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5622.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5622.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5622.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5622.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b560] >[ 5622.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b560] width 1920 pitch 7680 (/4 1920) >[ 5622.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5623.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5623.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5623.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5623.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5623.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5623.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5623.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5623.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5623.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5623.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5623.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5623.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5623.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5623.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5623.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5623.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5623.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5623.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5623.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5623.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5623.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5623.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5623.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5623.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5623.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5623.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5624.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5624.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5624.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5624.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5624.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5624.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5624.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5624.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5624.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5624.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5624.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5624.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5624.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5624.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5624.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5624.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5624.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5624.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5624.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5624.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5624.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5624.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5624.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5624.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5624.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5624.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5624.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5624.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5624.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5624.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5624.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5624.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5624.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5624.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5624.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5624.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5624.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5624.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5624.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5624.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5624.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5624.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5624.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5624.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5624.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5624.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5625.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5625.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5625.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5625.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5625.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5625.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5625.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5625.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5625.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5625.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5625.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5625.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5625.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5625.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5625.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5625.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5625.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5625.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5625.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5625.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5625.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5625.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5625.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5625.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5625.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5625.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5625.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5625.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5625.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5625.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5625.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5625.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5625.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5625.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5625.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5625.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5625.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5625.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5625.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5625.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5625.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5625.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5625.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5625.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5625.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5625.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5626.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5626.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5626.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5626.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5626.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5626.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5626.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5626.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5626.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5626.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5626.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5626.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5626.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5626.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5626.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5626.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5626.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5626.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5626.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5626.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5626.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5626.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5626.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5626.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5626.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5626.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5626.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5626.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5627.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5627.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5627.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5627.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5627.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5627.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5627.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5627.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5627.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5627.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5627.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5627.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5627.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5627.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5627.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5627.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5627.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5627.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5627.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5627.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5627.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5627.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5627.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5627.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5627.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5627.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5627.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5627.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5627.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5627.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5627.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5627.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5627.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5627.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5627.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5627.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5627.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5627.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5627.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5627.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5627.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5627.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5627.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5627.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5628.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5628.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5628.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5628.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5628.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5628.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5628.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5628.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5628.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5629.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5629.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5629.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5629.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5629.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5629.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5629.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5629.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5629.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5629.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5629.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5629.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5629.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5629.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5629.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5629.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5629.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5629.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5629.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5629.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5629.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5629.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5629.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5629.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5629.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5629.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5629.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5629.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5629.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5629.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5629.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5629.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5629.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5629.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5629.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5629.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5629.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5629.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5629.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5629.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5629.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5629.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5629.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5630.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5630.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5630.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5630.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5630.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5630.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5630.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5630.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5630.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5630.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5630.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5630.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5630.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5630.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5630.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5630.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5630.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5630.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5630.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5630.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5630.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5630.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5630.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5630.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5630.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5630.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5630.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5630.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5630.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5630.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5630.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5630.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5630.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5630.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5630.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5630.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5630.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5630.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5630.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5630.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5630.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5630.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5630.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5630.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5631.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5631.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5631.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5631.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5631.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5631.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5631.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5631.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5631.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5631.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5631.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5631.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5631.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5631.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5631.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5631.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5631.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5631.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5631.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5631.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5631.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5631.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5631.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5631.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5631.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5631.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5631.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5631.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5631.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5631.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5631.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5631.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5631.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5631.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5631.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5632.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5632.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5632.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5632.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5632.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5632.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5632.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5632.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5632.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5632.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5632.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5632.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5632.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5632.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5632.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5632.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5632.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5632.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5632.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5632.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5632.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5632.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5632.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5632.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5632.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5632.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5633.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5633.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5633.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5633.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5633.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5633.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5633.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5633.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5633.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5633.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5633.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5633.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5633.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5633.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5633.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5633.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5633.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5633.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5633.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5633.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5633.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5633.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5633.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5633.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5633.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5633.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5633.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5633.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5633.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5633.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5633.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5633.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5633.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5633.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5633.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5633.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5633.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5633.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5633.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5633.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5633.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5633.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5634.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5634.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5634.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5634.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5634.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5634.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5634.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5634.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5634.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5634.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5634.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5634.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5634.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5634.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5634.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5634.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5634.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5634.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5634.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5634.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5634.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5634.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5634.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5634.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5634.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5634.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5634.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5634.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5634.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5634.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5634.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5634.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5634.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5634.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5634.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5634.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5634.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5634.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5634.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5634.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5634.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5634.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5634.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5635.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5635.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5635.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5635.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5635.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5635.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5635.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5635.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5635.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5635.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5635.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5635.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5635.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5635.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5635.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5635.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5635.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5635.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5635.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5635.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5635.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5635.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5635.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5635.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5635.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5635.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5635.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5635.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5635.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5635.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5635.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5635.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5635.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5635.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5635.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5635.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5635.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5635.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5635.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5635.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5635.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5635.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5635.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5636.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5636.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5636.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5636.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5636.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5636.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5636.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5636.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5636.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5636.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5636.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5636.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5636.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5636.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5636.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5636.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5636.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5636.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5636.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5636.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5636.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5636.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5636.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5636.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5636.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5636.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5636.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5637.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5637.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5637.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5637.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5637.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5637.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5637.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5637.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5637.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5637.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5637.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5637.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5637.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5637.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5637.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5637.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5637.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5637.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5637.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5637.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5637.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5637.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5637.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5637.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5637.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5637.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5637.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5637.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5637.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5637.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5637.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5637.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5637.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5637.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5637.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5637.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5637.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5637.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5637.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5637.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5637.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5637.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5637.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5638.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5638.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5638.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5638.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5638.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5638.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5638.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5638.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5638.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5638.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5638.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5638.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5638.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5638.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5638.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5638.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5638.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5638.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5638.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5638.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5638.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5638.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5638.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5638.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5639.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5639.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5639.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5639.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5639.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5639.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5639.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5639.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5639.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5639.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5639.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5639.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5639.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5639.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5639.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5639.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5639.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5639.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5639.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5639.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5639.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5639.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5639.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5639.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5639.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5639.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5639.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5639.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5639.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5639.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5639.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5639.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5639.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5639.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5639.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5639.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5639.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5639.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5639.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5639.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5639.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5639.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5640.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5640.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5640.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5640.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5640.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5640.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5640.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5640.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5640.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5640.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5640.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5640.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5640.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5640.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5640.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5640.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5640.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5640.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5640.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5640.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5640.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5640.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5640.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5640.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5640.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5640.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5640.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5640.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5640.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5640.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5640.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5640.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5640.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5640.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5640.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5640.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5640.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5640.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5640.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5640.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5640.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5640.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5640.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5640.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5641.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5641.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5641.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5641.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5641.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5641.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5641.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5641.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5641.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5641.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5641.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5641.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5641.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5641.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5641.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5641.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5641.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5641.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5641.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5641.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5641.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5641.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5641.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5641.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5641.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5641.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5641.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5641.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5641.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5641.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5641.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5641.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5641.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5641.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5641.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5641.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5641.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5641.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5641.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5641.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5641.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5641.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5642.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5642.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5642.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5642.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5642.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5642.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5642.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5642.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5642.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5642.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5642.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5642.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5642.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5642.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5642.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5642.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5642.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5642.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5642.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5642.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5642.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5642.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5642.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5642.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5642.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5642.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5642.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5642.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5642.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5642.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5642.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5642.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5642.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5642.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5642.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5642.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5642.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5642.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5642.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5642.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5642.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5642.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5643.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5643.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5643.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5643.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5643.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5643.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5643.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5643.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5643.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5643.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5643.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5643.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5643.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5643.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5643.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5643.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5643.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5643.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5643.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5643.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5643.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5643.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5643.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5643.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5643.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5644.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5644.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5644.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5644.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5644.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5644.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5644.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5644.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5644.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5644.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5644.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5644.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5644.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5644.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5644.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5644.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5644.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5644.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5644.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5644.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5644.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5644.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5644.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5644.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5644.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5644.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5644.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5644.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5644.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5644.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5644.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5644.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5644.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5644.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5644.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5644.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5644.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5644.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5644.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5644.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5644.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5644.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5645.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5645.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5645.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5645.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5645.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5645.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5645.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5645.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5645.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5645.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5645.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5645.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5645.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5645.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5645.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5645.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5645.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5645.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5645.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5645.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5645.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5645.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5645.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5645.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5645.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5645.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5645.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5645.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5645.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5645.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5645.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5645.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5645.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5645.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5645.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5645.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5645.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5645.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5645.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5645.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5645.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5645.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5646.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5646.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5646.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5646.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5646.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5646.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5646.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5646.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5646.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5646.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5646.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5646.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5646.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5646.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5646.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5646.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5646.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5646.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5646.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5646.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5646.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5646.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5646.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5646.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5646.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5646.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5647.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5647.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5647.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5647.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5647.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5647.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5647.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5647.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5647.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5647.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5647.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5647.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5647.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5647.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5647.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5647.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5647.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5647.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5647.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5647.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5647.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5647.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5647.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5647.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5647.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5647.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5647.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5647.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5647.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5647.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5647.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5647.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5647.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5647.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5647.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5647.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5647.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5647.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5647.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5647.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5647.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5647.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5648.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5648.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5648.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5648.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5648.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5648.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5648.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5648.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5648.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5648.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5648.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5648.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5648.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5648.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5648.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5648.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5648.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5648.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5648.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5648.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5648.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5648.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5648.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5648.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5648.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5648.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5648.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5648.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5648.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5648.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5648.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5648.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5648.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5648.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5648.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5648.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5648.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5648.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5648.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5648.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5648.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5648.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5648.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5648.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5649.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5649.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5649.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5649.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5649.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5649.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5649.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5649.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5649.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5649.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5649.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5649.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5649.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5649.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5649.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5649.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5649.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5649.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5649.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5649.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5649.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5649.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5649.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5649.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5650.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5650.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5650.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5650.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5650.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5650.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5650.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5650.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5650.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5650.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5650.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5650.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5650.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5650.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5650.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5650.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5650.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5650.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5650.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5650.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5650.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5650.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5650.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5650.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5650.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5651.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5651.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5651.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5651.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5651.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5651.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5651.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5651.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5651.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5651.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5651.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5651.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5651.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5651.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5651.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5651.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5651.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5651.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5651.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5651.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5651.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5651.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5651.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5651.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5651.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5651.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5651.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5651.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5651.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5651.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5651.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5651.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5651.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5651.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5651.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5651.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5651.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5651.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5651.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5651.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5651.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5651.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5652.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5652.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5652.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5652.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5652.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5652.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5653.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5653.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5653.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5653.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5653.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5653.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5653.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5653.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5653.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5653.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5653.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5653.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5653.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5653.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5653.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5653.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5653.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5653.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5653.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5653.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5653.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5653.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5653.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5653.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5653.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5653.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5653.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5654.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5654.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5654.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5654.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5654.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5654.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5654.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5654.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5654.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5654.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5654.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5654.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5654.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5654.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5654.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5654.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5654.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5654.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5654.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5654.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5654.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5654.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5654.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5654.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5654.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5654.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5654.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5654.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5654.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5654.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5654.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5654.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5654.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5654.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5654.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5654.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5654.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5654.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5654.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5654.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5654.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5654.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5654.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5655.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5655.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5655.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5655.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5655.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5655.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5655.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5655.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5655.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5655.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5655.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5655.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5655.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5655.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5655.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5655.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5655.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5655.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5655.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5655.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5655.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5655.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5655.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5655.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5656.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5656.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5656.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5656.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5656.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5656.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5656.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5656.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5656.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5656.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5656.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5656.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5656.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5656.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5656.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5656.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5656.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5656.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5656.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5656.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5656.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5656.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5656.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5656.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5656.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5656.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5656.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5656.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5656.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5656.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5656.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5656.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5656.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5656.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5656.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5656.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5656.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5656.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5656.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5656.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5656.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5656.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5656.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5657.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5657.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5657.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5657.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5657.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5657.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5657.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5657.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5657.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5657.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5657.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5657.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5657.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5657.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5657.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5657.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5657.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5657.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5657.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5657.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5657.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5657.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5657.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5657.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5657.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5657.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5657.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5657.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5657.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5657.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5657.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5657.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5657.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5657.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5657.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5657.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5657.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5657.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5657.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5657.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5657.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5657.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5658.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5658.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5658.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5658.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5658.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5658.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5658.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5658.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5658.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5658.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5658.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5658.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5658.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5658.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5658.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5658.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5658.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5658.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5658.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5658.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5658.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5658.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5658.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5658.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5658.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5658.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5658.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5659.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5659.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5659.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5659.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5659.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5659.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5659.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5659.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5659.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5659.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5659.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5659.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5659.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5659.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5659.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5659.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5659.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5659.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5659.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5659.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5659.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5659.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5659.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5659.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5659.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5659.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5659.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5659.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5659.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5659.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5659.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5659.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5659.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5659.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5659.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5659.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5659.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5659.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5659.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5659.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5659.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5659.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5659.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5660.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5660.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5660.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5660.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5660.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5660.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5660.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5660.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5660.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5660.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5660.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5660.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5660.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5660.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5660.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5660.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5660.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5660.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5660.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5660.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5660.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5660.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5660.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5660.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5660.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5660.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5660.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5660.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5660.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5660.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5660.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5660.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5660.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5660.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5660.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5660.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5660.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5660.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5660.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5660.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5660.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5660.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5661.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5661.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5661.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5661.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5661.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5661.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5661.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5661.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5661.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5661.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5661.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5661.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5661.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5661.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5661.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5661.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5661.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5661.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5661.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5661.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5661.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5661.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5661.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5661.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5661.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5661.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5661.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5661.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5661.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5661.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5661.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5661.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5661.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5661.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5661.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5661.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5661.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5661.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5661.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5661.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5661.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5661.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5661.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5661.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5662.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5662.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5662.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5662.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5662.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5662.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5662.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5662.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5662.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5662.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5662.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5662.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5662.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5662.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5662.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5662.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5662.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5662.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5662.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5662.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5662.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5662.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5662.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5662.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5662.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5662.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5662.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5662.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5662.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5662.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5662.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5662.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5662.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5662.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5662.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5662.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5662.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5662.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5662.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5662.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5662.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5662.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5663.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5663.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5663.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5663.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5663.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5663.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5663.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5663.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5663.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5663.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5663.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5663.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5663.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5663.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5663.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5663.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5663.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5663.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5663.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5663.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5663.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5663.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5663.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5663.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5663.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5663.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5663.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5663.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5663.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5663.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5663.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5663.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5663.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5663.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5663.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5663.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5663.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5663.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5663.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5663.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5664.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeedb0] >[ 5664.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeedb0] width 1920 pitch 7680 (/4 1920) >[ 5664.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5664.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5664.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5664.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5664.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5664.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5664.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5664.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5664.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5664.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5664.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5664.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5664.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5664.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5664.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5664.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5664.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5664.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5664.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5664.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5664.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5664.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5664.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5664.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5664.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5664.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5664.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5664.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5664.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5664.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5664.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5664.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5664.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5664.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5664.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5664.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5664.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5664.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5664.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5664.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5665.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5665.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5665.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5665.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5665.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5665.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5665.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5665.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5665.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5665.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5665.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5665.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5665.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5665.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5665.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5665.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5665.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5665.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5665.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5665.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5665.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5665.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5665.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5665.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5665.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5665.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5665.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5665.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5665.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5665.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5665.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5665.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5665.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5665.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5665.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5665.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5665.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5665.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5665.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5665.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5666.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5666.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5666.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5666.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5666.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5666.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5666.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5666.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5666.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5666.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5666.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5666.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5666.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5666.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5666.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5666.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5666.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5666.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5666.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5666.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5666.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5666.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5666.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5666.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5666.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5666.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5666.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5666.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5666.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5666.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5666.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5666.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5666.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5666.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5666.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5666.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5666.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5666.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5666.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5666.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5666.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5666.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5667.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5667.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5667.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5667.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5667.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5667.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5667.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5667.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5667.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5667.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5667.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5667.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5667.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5667.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5667.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5667.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5667.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5667.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5667.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5667.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5667.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5667.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5667.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5667.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5667.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5667.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5668.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5668.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5668.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5668.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5668.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5668.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5668.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5668.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5668.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5668.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5668.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5668.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5668.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5668.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5668.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5668.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5668.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5668.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5668.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5668.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5668.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5668.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5668.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5668.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5668.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5668.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5668.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5668.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5668.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5668.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5668.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5668.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5668.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5668.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5668.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5668.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5668.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5668.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5668.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5668.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5669.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5669.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5669.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5669.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5669.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5669.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5669.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5669.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5669.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5669.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5669.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5669.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5669.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5669.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5669.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5669.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5669.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5669.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5669.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5669.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5669.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5669.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5669.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5669.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5669.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5669.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5669.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5669.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5669.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5669.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5669.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5669.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5669.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5669.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5669.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5669.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5669.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5669.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5669.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5669.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5670.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5670.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5670.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5670.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5670.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5670.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5670.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5670.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5670.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5670.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5670.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5670.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5670.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5670.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5670.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5670.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5670.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5670.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5670.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5670.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5670.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5670.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5670.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5670.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5671.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5671.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5671.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5671.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5671.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5671.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5671.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5671.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5671.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5671.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5671.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5671.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5671.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5671.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5671.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5671.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5671.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5671.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5671.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5671.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5671.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5671.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5671.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5671.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5671.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5671.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5671.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5671.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5671.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5671.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5671.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5671.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5671.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5671.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5671.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5671.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5671.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5671.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5671.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5671.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5671.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5671.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5672.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585d30] >[ 5672.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585d30] width 1920 pitch 7680 (/4 1920) >[ 5672.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5672.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5672.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5672.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5672.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5672.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5672.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5672.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5672.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5672.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5672.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5672.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5672.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5672.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5672.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5672.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5672.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5672.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5672.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5672.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5672.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5672.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5672.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5672.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5672.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5672.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5672.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5672.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5672.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5672.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5672.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5672.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5673.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5673.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5673.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5673.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5673.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5673.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5673.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5673.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5673.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5673.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5673.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5673.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5673.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5673.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5673.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5673.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5673.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5673.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5673.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5673.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5673.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5673.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5673.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5673.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5673.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5673.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5673.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5673.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5673.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5673.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5673.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5673.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5673.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5673.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5673.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5673.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5673.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5673.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5673.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5673.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5674.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5674.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5674.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5674.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5674.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5674.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5674.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5674.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5674.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5674.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5674.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5674.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5674.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5674.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5674.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5674.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5674.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5674.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5674.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5674.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5674.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5674.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5674.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5674.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5674.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5674.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5674.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5674.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5674.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5674.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5674.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5674.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5674.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5674.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5674.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5674.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5674.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5674.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5674.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5674.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5674.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5674.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5674.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5675.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5675.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5675.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5675.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5675.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5675.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5675.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5675.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5675.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5675.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5675.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5675.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5675.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5675.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5675.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5675.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5675.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5675.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5675.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5675.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5675.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5675.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5675.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5675.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5675.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5675.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5675.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5675.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5675.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5675.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5675.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5675.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5675.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5675.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5675.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5675.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5675.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5675.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5675.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5675.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5675.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5675.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5676.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5676.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5676.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5676.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5676.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5676.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5676.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5676.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5676.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5676.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5676.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5676.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5676.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5676.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5676.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5676.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5676.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5676.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5676.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5676.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5676.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5676.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5676.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5676.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5676.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5676.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5677.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5677.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5677.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5677.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5677.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5677.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5677.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5677.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5677.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5677.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5677.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5677.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5677.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5677.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5677.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5677.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5677.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5677.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5677.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5677.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5677.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5677.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5677.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5677.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5677.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5677.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5677.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5677.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5677.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5677.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5677.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5677.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5677.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5677.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5677.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5677.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5677.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5677.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5677.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5677.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5677.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5677.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5677.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5677.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5678.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5678.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5678.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5678.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5678.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5678.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5678.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5678.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5678.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5678.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5678.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5678.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5678.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5678.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5678.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5678.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5678.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5678.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5678.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5678.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5678.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5678.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5678.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5678.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5678.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5678.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5678.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5678.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5678.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5678.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5678.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5678.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5678.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5678.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5678.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5678.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5678.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5678.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5678.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5678.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5678.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5678.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5678.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5679.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5679.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5679.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5679.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5679.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5679.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5679.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5679.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5679.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5679.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5679.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5679.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5679.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5679.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5679.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5679.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5679.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5679.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5679.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5679.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5679.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5679.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5679.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5679.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5679.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5679.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5679.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5679.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5679.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5679.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5679.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5679.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5679.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5679.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5679.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5679.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5679.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5679.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5679.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5679.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5679.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5679.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5679.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5679.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5679.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5679.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5680.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5680.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5680.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5680.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5680.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5680.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5680.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5680.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5680.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5680.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5680.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5680.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5680.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5680.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5680.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5680.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5680.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5680.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5680.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5680.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5680.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5680.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5680.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5680.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5680.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5680.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5680.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5680.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5680.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5680.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5680.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5680.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5680.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5680.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5680.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5680.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5680.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5680.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5680.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5680.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5680.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5680.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5680.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5680.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5680.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5680.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5681.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5681.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5681.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5681.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5681.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5681.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5681.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5681.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5681.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5681.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5681.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5681.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5681.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5681.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5681.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5681.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5681.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5681.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5681.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5681.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5681.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5681.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5681.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5681.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5681.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5681.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5681.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5682.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5682.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5682.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5682.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5682.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5682.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5682.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5682.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5682.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5682.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5682.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5682.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5682.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5682.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5682.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5682.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5682.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5682.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5682.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5682.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5682.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5682.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5682.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5682.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5682.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5682.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5682.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5682.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5682.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5682.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5682.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5682.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5682.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5682.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5682.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5682.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5682.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5682.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5683.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5683.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5683.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5683.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5683.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5683.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5683.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5683.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5683.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5683.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5683.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5683.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5683.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5683.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5683.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5683.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5683.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5683.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5683.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5683.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5683.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5683.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5683.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5683.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5683.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5683.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5683.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5683.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5683.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5683.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5683.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5683.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5683.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5683.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5683.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5683.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5683.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5684.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5684.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5684.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5684.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5684.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5684.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5684.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5684.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5684.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5684.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5684.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5684.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5684.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5684.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5684.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5684.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5685.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5685.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5685.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5685.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5685.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5685.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5685.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5685.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5685.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5685.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5685.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5685.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5685.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5685.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5685.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5685.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5685.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5685.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5685.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5685.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5686.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5686.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5686.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5686.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5686.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5686.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5686.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5686.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5686.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5686.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5686.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5686.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5686.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5686.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5686.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5686.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5686.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5686.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5686.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5686.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5686.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5686.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5686.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5686.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5686.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5686.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5686.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5686.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5686.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5686.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5686.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5686.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5686.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5686.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5686.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5686.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5686.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5686.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5687.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5687.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5687.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5687.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5687.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5687.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5687.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5687.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5687.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5687.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5687.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5687.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5687.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5687.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5687.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5687.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5687.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5687.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5687.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5687.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5687.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5687.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5687.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5687.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5687.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5687.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5687.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5687.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5687.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5687.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5687.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5687.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5687.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5687.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5687.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5687.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5688.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5688.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5688.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5688.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5688.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5688.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5688.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5688.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5688.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5688.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5688.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5688.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5688.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4067e00] >[ 5688.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4067e00] width 1920 pitch 7680 (/4 1920) >[ 5688.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5688.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5688.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5688.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5688.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5688.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5688.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5688.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5688.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5688.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5688.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5688.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5688.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5688.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5688.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5688.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5688.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5688.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5688.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5688.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5688.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5688.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5689.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5689.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5689.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5689.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5689.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5689.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5689.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5689.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5689.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5689.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5689.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5689.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5689.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5689.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5689.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d040] >[ 5689.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d040] width 1920 pitch 7680 (/4 1920) >[ 5689.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x29f8040] >[ 5689.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x29f8040] width 1920 pitch 7680 (/4 1920) >[ 5689.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5689.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5689.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5689.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5689.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5689.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5689.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5689.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5689.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5689.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5689.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5689.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5689.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5689.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5689.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5689.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5689.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5689.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5689.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5689.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5689.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5689.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5689.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5689.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5689.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5689.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5689.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5689.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5689.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5689.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5689.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5689.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5689.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5690.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5690.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5690.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5690.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4811d50] >[ 5691.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4811d50] width 1920 pitch 7680 (/4 1920) >[ 5691.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5691.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4811d50] >[ 5691.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4811d50] width 1920 pitch 7680 (/4 1920) >[ 5691.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5691.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5691.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4811d50] >[ 5691.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4811d50] width 1920 pitch 7680 (/4 1920) >[ 5691.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5691.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5691.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5691.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5691.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5691.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5691.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5691.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5691.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4811d50] >[ 5691.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4811d50] width 1920 pitch 7680 (/4 1920) >[ 5691.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5691.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5691.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4811d50] >[ 5691.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4811d50] width 1920 pitch 7680 (/4 1920) >[ 5691.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5691.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5691.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5691.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5691.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5691.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5691.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5691.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5691.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5691.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5691.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5691.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5691.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5691.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5691.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5691.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5691.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5691.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5691.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5691.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5692.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5692.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5692.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5692.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5692.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5692.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5692.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5692.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5692.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5692.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5692.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5692.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5692.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5692.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5692.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5692.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5692.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5692.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5692.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5692.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5692.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5692.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5692.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5692.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5692.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5692.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5692.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5692.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5692.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5692.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5692.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5692.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5693.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5693.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5693.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5693.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5693.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5693.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5693.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5693.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5693.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5693.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5693.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5693.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5693.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5693.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5693.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5693.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5693.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5693.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5693.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5693.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5693.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5693.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5693.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5693.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5693.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5693.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5693.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5693.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5693.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5693.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5693.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5694.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5694.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5694.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5694.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5694.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5694.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5694.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5694.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5694.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5694.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5694.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5694.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5695.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5695.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48441f0] >[ 5695.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48441f0] width 1920 pitch 7680 (/4 1920) >[ 5695.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5695.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5695.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48441f0] >[ 5695.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48441f0] width 1920 pitch 7680 (/4 1920) >[ 5695.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5695.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5695.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48441f0] >[ 5695.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48441f0] width 1920 pitch 7680 (/4 1920) >[ 5695.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5695.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5695.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48441f0] >[ 5695.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48441f0] width 1920 pitch 7680 (/4 1920) >[ 5695.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5695.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5695.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5695.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5695.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48441f0] >[ 5695.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48441f0] width 1920 pitch 7680 (/4 1920) >[ 5695.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5695.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5695.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48441f0] >[ 5695.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48441f0] width 1920 pitch 7680 (/4 1920) >[ 5695.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5695.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5695.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48441f0] >[ 5695.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48441f0] width 1920 pitch 7680 (/4 1920) >[ 5695.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5695.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5695.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48441f0] >[ 5695.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48441f0] width 1920 pitch 7680 (/4 1920) >[ 5695.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5695.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5695.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5695.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5695.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5695.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5695.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5695.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5695.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5695.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5695.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5695.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5695.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4843c80] >[ 5695.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4843c80] width 1920 pitch 7680 (/4 1920) >[ 5695.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5695.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5696.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4843c80] >[ 5696.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4843c80] width 1920 pitch 7680 (/4 1920) >[ 5696.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5696.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5696.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4843c80] >[ 5696.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4843c80] width 1920 pitch 7680 (/4 1920) >[ 5696.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5696.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5696.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5696.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5696.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5696.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5696.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5696.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5696.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5696.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5696.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5696.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5696.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5696.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5696.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5696.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5696.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5696.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5696.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5696.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5696.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5696.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5696.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5696.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5696.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5696.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5696.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5696.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5696.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5696.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5696.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5696.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5696.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5696.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5696.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5696.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5696.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5696.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5696.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5696.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5696.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5696.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5697.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5697.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5697.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5697.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5697.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5697.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5697.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5697.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5697.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5697.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5697.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5697.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5697.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5697.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5697.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5697.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5697.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5697.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5697.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5697.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5697.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5697.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5697.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5697.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5697.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5697.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5697.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5698.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5698.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5698.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5698.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5698.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5699.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5699.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5699.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5699.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5699.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5699.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5699.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5699.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5699.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5699.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5699.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5699.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5699.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5699.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5699.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5699.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5699.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5699.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5699.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5699.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5699.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5699.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5699.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5699.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5699.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5699.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5699.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5699.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5700.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5700.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5700.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5700.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5700.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5700.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5700.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5700.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5700.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5700.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5700.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5700.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5700.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5700.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5700.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5700.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5700.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5700.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5700.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5700.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5700.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5700.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5700.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5700.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5700.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5700.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5700.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5700.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5700.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5700.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5700.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5700.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5700.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5700.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5700.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5700.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5700.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5700.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5700.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5700.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5700.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5700.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5700.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5700.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5701.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5701.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5701.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5701.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5701.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5701.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5701.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5701.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5701.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5701.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5701.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5701.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5701.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5701.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5701.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5701.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5701.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5701.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5701.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5701.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5701.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5701.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5701.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5701.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5701.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5701.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5701.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5701.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5701.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5702.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5702.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5702.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5702.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5702.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5702.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5702.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5702.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5702.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5702.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5702.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5702.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5702.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5702.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5702.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5702.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5702.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5702.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5702.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5702.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5702.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5702.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5702.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5702.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5702.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5702.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5702.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5702.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5702.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5702.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5702.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5702.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5702.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5702.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5702.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5702.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5702.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5702.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5702.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5702.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5702.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5702.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5702.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5703.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5703.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5703.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5703.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5703.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5703.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5703.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5703.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5703.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5703.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5703.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5703.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5703.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5703.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5703.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5703.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5703.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5703.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5703.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5703.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5703.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5703.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5703.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5703.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5703.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5703.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5703.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5704.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5704.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5704.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5704.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5704.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5704.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5704.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5704.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5704.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5704.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5704.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5705.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5705.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5705.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5705.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5705.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5705.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5705.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5705.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5705.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5705.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5705.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5705.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5705.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5705.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5705.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5705.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5705.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5705.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5705.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5705.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5705.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5705.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5705.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5705.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5705.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5705.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5705.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5705.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5705.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5705.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5705.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5705.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5705.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5705.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5705.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5705.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5705.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5705.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5705.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5705.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5705.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5705.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5706.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5706.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5706.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5706.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5706.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5706.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5706.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5706.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5706.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5706.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5706.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5706.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5706.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5706.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5706.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5706.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5706.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5706.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5706.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5706.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5706.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5706.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5706.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5706.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5706.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5706.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5706.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5706.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5706.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5706.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5706.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5706.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5706.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5706.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5706.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5706.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5706.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5706.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5706.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5706.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5706.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5707.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5707.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5707.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5707.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5707.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5707.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5707.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5707.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5707.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5707.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5707.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5707.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5707.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5707.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5707.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5707.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5707.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5707.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5707.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5707.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5707.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5707.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5707.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5708.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5708.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5708.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5708.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5708.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5708.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5708.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5708.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5708.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5708.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5708.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5708.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5708.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5708.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5708.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5708.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5708.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5708.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5708.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5708.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5708.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5708.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5708.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5709.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5709.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5709.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5709.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5709.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5709.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5709.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5710.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5710.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5710.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5710.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5710.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5710.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5710.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5710.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5710.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5710.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5710.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5710.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5710.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5710.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5710.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5710.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5710.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5710.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5710.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5710.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5710.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5710.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5710.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5710.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5710.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5710.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5710.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5710.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5710.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5710.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5710.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5710.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5710.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5710.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5710.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5710.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5710.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5710.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5710.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5711.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5711.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5711.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5711.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5711.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5711.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5711.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5711.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5711.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5711.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5711.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5711.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5711.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5711.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5711.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5711.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5711.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5711.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5711.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5711.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5711.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5711.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5711.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5711.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5711.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5711.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5711.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5711.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5711.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5711.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5711.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5711.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5711.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5711.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5711.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5711.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5711.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5711.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5711.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5711.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5712.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5712.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5712.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5712.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5712.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5712.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5712.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5712.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5712.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5712.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5712.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5712.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5712.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5712.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5712.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5712.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5712.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5712.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5712.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5712.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5712.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5712.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5713.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5713.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5713.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5713.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5713.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5713.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5713.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5713.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5713.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5713.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5713.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5713.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5713.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5713.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5713.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5713.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5713.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5713.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5713.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5713.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5713.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5713.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5713.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5713.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5713.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5713.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5713.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5713.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5713.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5713.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5713.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5713.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5714.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5714.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5714.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5714.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5714.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5714.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5714.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5714.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5714.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5714.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5714.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5714.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5714.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5714.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5714.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5714.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5714.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5714.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5714.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5714.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5714.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5714.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5714.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5714.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5714.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5714.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5714.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5714.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5714.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5714.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5714.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5714.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5714.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5714.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5714.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5714.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5714.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5714.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5715.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5715.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5715.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5715.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5715.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5715.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5715.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5715.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5715.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5715.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5715.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5715.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5715.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5715.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5715.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5715.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5715.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5715.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5715.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5715.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5715.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5715.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5715.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5715.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5715.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5715.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5715.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5715.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5715.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5715.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5715.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5715.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5715.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5715.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5715.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5715.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5715.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5715.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5716.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5716.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5716.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5716.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5716.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5716.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5716.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5716.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5716.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5716.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5716.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5716.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5716.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5716.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5716.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5716.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5716.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5716.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5716.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5716.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5716.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5716.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5716.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5716.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5716.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5716.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5716.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5716.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5716.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5716.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5716.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5716.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5717.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5717.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5717.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5717.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5717.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5717.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5717.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5717.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5717.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5717.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5717.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5717.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5717.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5717.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5717.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5717.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5717.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5717.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5717.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5717.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5717.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5717.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5717.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5718.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5718.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5718.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5718.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5718.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5718.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5718.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5718.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5718.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5718.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5718.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5718.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5718.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5718.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5718.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5718.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5718.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5718.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5718.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5718.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5718.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5718.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5718.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5718.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5718.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5718.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5718.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5718.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5718.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5718.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5718.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5718.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5718.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5718.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5718.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5718.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5718.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5718.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5718.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5719.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5719.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5719.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5719.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5719.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5719.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5719.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5719.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5719.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5719.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5719.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5719.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5719.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5719.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5719.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5719.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5719.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5719.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5719.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5719.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5719.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5720.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5720.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5720.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5720.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5721.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5721.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5721.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5721.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5721.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5721.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5721.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5721.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5721.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5721.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5721.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5721.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5721.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5721.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5721.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5721.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5721.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5721.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5721.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5721.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5721.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5721.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5721.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5721.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5721.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5721.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5721.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5721.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5721.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5721.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5721.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5721.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5721.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5721.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5721.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5721.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5721.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5721.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5721.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5721.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5722.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5722.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5722.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5722.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5722.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5722.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5722.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5722.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5722.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5722.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5722.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5722.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5722.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5722.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5722.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5722.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5722.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5722.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5722.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5722.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5722.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5722.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5722.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5722.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5722.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5722.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5722.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5722.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5722.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5722.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5722.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5722.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5722.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5722.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5722.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5722.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5722.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5722.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5722.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5722.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5722.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5723.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5723.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5723.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5723.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5723.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5723.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5723.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5723.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5723.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5723.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5723.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5723.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5723.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5723.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5723.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5723.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5723.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5723.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5723.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5723.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5723.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5723.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5723.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5723.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5723.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5723.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5723.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5723.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5723.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5723.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5723.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5723.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5724.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5724.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5724.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5724.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5724.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5724.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5724.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5724.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5724.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5724.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5724.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5724.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5724.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5724.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5724.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5724.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5724.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5724.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5724.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5724.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5724.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5724.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5725.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5725.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5725.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5725.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5725.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5725.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5726.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5726.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5726.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5726.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5726.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5726.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5726.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5726.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5726.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5726.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5726.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5726.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5726.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5726.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5726.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5726.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5726.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5726.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5726.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5726.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5726.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5726.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5727.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5727.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5727.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5727.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5727.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5727.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5727.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5727.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5727.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5727.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5727.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5727.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5727.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5727.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5727.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5727.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5727.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5727.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5727.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5727.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5727.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5727.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5727.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5727.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5727.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5728.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5728.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5728.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5728.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5728.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5728.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5728.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5728.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5728.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5728.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5728.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5728.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5728.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5728.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5728.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5728.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5728.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5728.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5728.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5728.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5728.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5728.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5728.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5728.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5728.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5728.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5728.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5728.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5728.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5728.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5728.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5728.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5728.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5728.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5728.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5728.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5728.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5728.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5728.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5728.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5729.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5729.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5729.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5729.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5729.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5729.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5729.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5729.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5729.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5729.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5729.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5729.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5729.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5729.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5729.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5729.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5729.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5729.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5729.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5729.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5729.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5730.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5730.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5730.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5730.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5731.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5731.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5731.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5731.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5731.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5731.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5731.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5731.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5731.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5731.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5731.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5731.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5731.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5731.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5731.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5731.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5731.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5731.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5731.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5731.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5731.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5731.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5731.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5731.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5731.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5731.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5731.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5731.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5731.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5731.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5731.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5731.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5731.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5731.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5731.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5731.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5731.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5731.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5731.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5731.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5732.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5732.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5732.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5732.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5732.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5732.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5732.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5732.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5732.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5732.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5732.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5732.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5732.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5732.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5732.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5732.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5732.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5732.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5732.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5732.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5732.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5732.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5732.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5732.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5732.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5732.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5732.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5732.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5732.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5732.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5732.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5732.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5732.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5732.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5732.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5732.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5732.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5732.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5732.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5732.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5733.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5733.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5733.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5733.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5733.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5733.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5733.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5733.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5733.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5733.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5733.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5733.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5733.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5733.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5733.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5733.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5733.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5733.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5733.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5733.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5733.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5733.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5733.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5733.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5733.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5733.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5733.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5733.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5733.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5733.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5733.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5733.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5733.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5733.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5733.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5733.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5733.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5733.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5733.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5733.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5733.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5733.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5734.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5734.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5734.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5734.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5734.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5734.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5734.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5734.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5734.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5734.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5734.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5734.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5734.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5734.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5734.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5734.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5734.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5734.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5734.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5734.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5734.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5734.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5734.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5735.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5735.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5735.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5735.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5735.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5735.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5735.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5735.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5735.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5735.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5735.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5735.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5735.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5735.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5735.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5735.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5735.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5735.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5735.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5735.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5735.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5735.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5735.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5735.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5735.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5736.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5736.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5736.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5736.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5736.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5736.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5736.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5736.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5736.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5736.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5736.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5736.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5736.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5736.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5736.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5736.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5736.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5736.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5736.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5736.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5736.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5736.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5736.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5736.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5736.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5736.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5736.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5736.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5736.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5736.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5736.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5736.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5736.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5736.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5736.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5736.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5736.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5736.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5736.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5736.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5736.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5736.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5737.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5737.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5737.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5737.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5737.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5737.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5737.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5737.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5737.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5737.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5737.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5737.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5737.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5737.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5737.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5737.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5737.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5737.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5737.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5737.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5737.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5737.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5737.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5737.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5737.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5738.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5738.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5738.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5738.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5738.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5738.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5738.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5738.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5738.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5738.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5738.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5738.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5738.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5738.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5738.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5738.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5738.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5738.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5738.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5738.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5738.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5738.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5738.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5738.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5738.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5739.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5739.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4846a00] >[ 5739.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4846a00] width 1920 pitch 7680 (/4 1920) >[ 5739.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5739.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5739.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5739.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5739.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4846490] >[ 5739.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4846490] width 1920 pitch 7680 (/4 1920) >[ 5740.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5740.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5740.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5740.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5740.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5740.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5740.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5740.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5740.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5740.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5740.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5740.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5740.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5740.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5740.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5740.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5740.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5740.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5740.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5740.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5740.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5740.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5740.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5740.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5740.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5741.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5741.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5741.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5741.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5741.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5741.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5741.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5741.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5741.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5742.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5742.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5742.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5742.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5743.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5743.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5743.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5743.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5743.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5743.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5743.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5743.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5743.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5743.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5743.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5743.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5743.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5743.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5743.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5743.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5743.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5743.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5743.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5743.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5743.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5743.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5743.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5743.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5744.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5744.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5744.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5744.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5744.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5744.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5744.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5744.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5744.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5744.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5744.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5744.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5744.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5744.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5744.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5744.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5744.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5744.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5744.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5744.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5744.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5744.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5744.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5744.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5744.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5744.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5744.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5744.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5744.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5744.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5744.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5744.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5744.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5744.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5744.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5744.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5744.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5744.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5744.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5744.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5744.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5744.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5744.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5744.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5745.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5745.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5745.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5745.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5745.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5745.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5745.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5745.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5745.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5745.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5745.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5745.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5745.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5745.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5745.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5745.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5745.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5745.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5745.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5745.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5745.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5745.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5745.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5745.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5745.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5746.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5746.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5746.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5746.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5746.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5746.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5746.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5746.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5746.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5746.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5746.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5746.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5746.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5746.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5746.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5746.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5746.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5746.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5746.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5746.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5746.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5746.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5746.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5746.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5747.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5747.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5747.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5747.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5747.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5747.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5747.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5747.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5747.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5747.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5747.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5747.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5747.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5747.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5747.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5747.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5747.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5747.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5747.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5747.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5747.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5747.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5747.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5747.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5747.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5747.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5747.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5747.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5747.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5747.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5747.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5747.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5747.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5747.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5747.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5747.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5747.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5747.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5747.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5747.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5747.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5747.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5748.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5748.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5748.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5748.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5748.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5748.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5748.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5748.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5748.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5748.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5748.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5748.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5748.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5748.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5748.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5748.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5748.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5748.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5748.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5748.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5748.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5748.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5748.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5748.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5748.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5749.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5749.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5749.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5749.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5749.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5749.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5749.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5749.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5749.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5749.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5749.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5749.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5749.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5749.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5749.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5749.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5749.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5749.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5749.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5749.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5749.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5749.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5749.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5749.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5749.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5749.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4853ad0] >[ 5749.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4853ad0] width 1920 pitch 7680 (/4 1920) >[ 5749.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5749.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5749.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5749.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5749.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5749.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5749.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5749.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5749.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5749.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5749.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5749.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5749.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5749.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5749.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5749.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5749.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5749.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5750.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5750.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5750.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5750.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5750.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5750.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5750.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5750.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5750.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5750.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5750.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5750.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5750.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5750.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5750.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5750.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5750.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5750.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5750.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5750.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5750.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5750.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5750.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5750.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5750.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5750.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5751.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5751.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5751.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5751.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5751.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5751.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5751.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5751.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5751.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5751.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5751.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5751.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5751.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5751.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5751.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5751.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5751.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5751.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5751.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5751.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5751.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5751.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5751.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5751.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5751.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5751.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5751.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5751.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5751.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5751.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5752.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5752.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5752.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5752.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5752.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5752.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5752.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5752.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5752.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5752.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5752.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5752.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5752.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5753.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5753.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5753.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5753.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5753.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5753.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5753.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5753.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5753.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5753.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5753.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5753.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5753.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5753.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5753.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5754.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5754.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5754.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5754.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5754.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5754.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5754.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5754.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5754.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5755.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5755.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5755.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5755.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5755.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5755.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5755.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5755.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5755.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5755.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5755.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5755.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5755.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5756.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5756.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5756.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5756.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5756.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5756.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5756.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5757.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5757.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5757.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5757.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5757.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5758.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5758.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5758.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5758.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5758.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5758.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5758.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5758.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5758.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5758.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5758.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5758.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5758.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5758.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5759.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5759.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5759.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5759.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5759.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5759.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5759.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5759.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5759.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5759.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5759.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5759.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5759.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5759.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5759.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5759.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5759.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5759.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5759.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5759.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5759.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5759.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5759.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5759.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5759.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5759.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5759.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5759.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5760.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5760.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5760.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5760.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5760.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5760.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5760.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5760.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5760.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5760.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5760.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5760.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5760.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5760.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5760.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5760.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5760.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5760.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5761.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5761.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5761.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5761.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5761.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5761.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5761.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5761.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5761.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5761.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5761.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5761.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5761.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5761.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5761.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5761.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5761.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5761.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5761.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5761.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5761.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5761.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5761.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5761.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5761.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5761.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5761.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5761.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5761.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5761.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5761.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5762.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5762.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5762.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5762.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5762.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5762.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5762.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5762.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5762.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5762.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5762.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5762.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5762.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5762.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5762.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5762.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5762.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5762.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5762.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5762.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5762.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5762.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5762.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5762.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5762.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5762.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5762.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5762.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5762.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5763.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5763.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5763.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5763.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5763.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5763.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5764.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5764.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5764.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5764.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5764.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5764.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5764.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5764.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5764.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5764.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5764.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5764.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5764.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5764.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5764.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5764.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5764.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5764.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5764.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5764.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5764.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5764.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5764.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5764.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5764.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5764.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5764.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5764.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5764.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5764.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5764.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5764.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5764.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5765.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5765.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5765.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5765.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5765.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5765.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5765.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5765.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5766.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5766.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5766.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5766.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5766.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5766.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5766.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5766.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5766.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5766.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5766.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5766.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5766.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5766.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5766.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5766.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5766.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5766.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5766.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5766.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5766.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5766.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5766.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5766.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5766.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5766.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5766.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5766.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5766.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5767.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5767.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5767.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5767.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5767.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5767.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5767.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5767.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5767.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5767.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5767.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5767.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5767.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5767.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5767.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5767.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5767.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5767.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5767.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5767.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5767.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5767.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5767.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5767.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5767.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5767.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5767.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5767.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5767.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5767.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5767.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5768.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5768.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5768.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5768.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5768.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5768.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5768.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5768.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5768.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5769.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5769.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5769.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5769.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5770.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5770.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5770.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5770.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5770.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5770.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5770.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5770.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5770.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5770.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5770.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5770.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5770.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5770.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5770.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5770.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5770.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5770.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5770.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5770.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5770.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5770.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5770.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5770.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5770.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5770.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5770.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5770.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5770.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5771.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5771.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5771.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5771.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5771.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5771.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5771.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5771.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5771.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5771.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5771.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5771.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5771.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5771.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5771.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5771.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5771.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5771.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5771.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5771.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5771.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5771.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5771.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5771.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5772.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5772.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5772.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5772.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5772.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5772.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5772.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5772.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5772.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5772.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5772.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5772.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5772.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5772.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5772.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5772.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5772.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5772.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5772.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5772.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5772.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5772.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5772.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5772.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5772.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5772.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5772.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5772.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5772.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5772.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5772.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5772.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5772.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5772.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5772.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5772.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5772.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5772.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5772.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5772.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5772.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5772.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5772.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5773.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5773.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5773.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5773.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5774.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5774.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5774.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5774.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5774.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5774.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5774.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5774.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5774.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5774.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5774.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5774.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5774.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5774.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5774.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5774.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5774.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5774.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5774.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5774.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5774.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5774.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5774.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5775.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5775.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5775.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5775.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5775.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5775.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5775.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5775.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5775.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5775.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5775.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5775.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5775.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5775.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5775.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5775.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5775.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5775.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5775.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5775.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5775.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5775.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5775.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5775.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5775.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5775.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5775.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5775.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5775.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5775.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5775.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5775.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5775.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5775.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5775.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5775.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5775.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5775.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5775.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5775.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5775.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5775.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5776.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5776.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5776.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5776.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5776.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5776.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5776.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5776.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5776.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5776.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5776.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5776.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5776.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5776.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5776.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5776.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5776.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5776.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5776.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5776.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5776.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5776.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5776.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5776.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5776.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5776.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5776.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5776.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5776.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5776.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5776.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5776.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5776.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5776.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5776.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5776.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5776.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5776.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5776.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5776.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5776.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5777.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5777.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5777.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5777.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5777.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5777.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5777.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5777.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5777.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5777.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5777.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5777.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5777.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5777.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5777.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5777.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5777.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5777.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5777.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5777.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5777.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5777.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5777.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5777.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5777.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5777.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5777.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5777.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5777.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5777.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5777.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5777.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5777.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5777.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5777.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5777.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5777.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5777.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5777.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5777.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5777.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5778.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5778.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5778.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5778.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5778.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5778.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5778.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5778.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5778.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5778.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5778.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5778.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5778.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5778.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5778.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5778.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5778.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5778.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5778.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5778.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5778.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5778.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5778.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5778.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5778.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5778.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5779.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5779.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5779.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5779.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5779.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5780.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5780.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5780.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5780.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5780.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5780.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5780.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5780.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5780.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5780.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5780.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5780.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5780.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5780.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5780.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5780.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5780.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5780.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5780.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5780.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5780.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5780.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5780.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5780.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5780.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5780.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5780.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5780.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5780.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5780.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5780.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5780.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5780.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5780.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5780.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5780.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5780.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5780.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5780.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5780.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5780.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5780.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5781.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5781.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5781.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5781.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5781.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5781.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5782.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5782.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5782.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5782.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5783.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5783.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5783.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5783.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5783.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5784.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5784.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5784.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5784.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5784.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5784.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5784.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5784.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5784.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5784.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5784.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5784.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5784.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5784.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5784.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5784.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5784.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5784.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5784.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5784.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5784.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5784.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5784.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5785.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5785.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5785.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5785.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5785.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5785.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5785.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5786.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5786.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5786.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5786.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5786.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5786.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5786.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5786.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5786.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5786.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5786.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5786.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5786.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5786.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5786.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5786.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5786.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5786.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5786.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5786.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5786.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5786.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5786.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5786.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5786.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5786.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5786.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5786.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5786.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5786.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5786.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5786.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5786.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5786.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5787.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5787.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5787.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5787.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5787.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5787.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5787.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5787.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5787.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5787.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5787.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5787.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5787.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5787.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5787.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5787.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5787.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5787.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5787.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5787.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5787.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5787.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5787.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5787.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5787.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5787.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5787.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5787.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5787.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5787.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5787.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5787.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5788.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5788.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5788.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5788.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5788.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5788.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5788.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5788.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5788.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5788.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5788.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5788.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5788.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5788.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5788.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5788.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5788.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5788.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5788.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5788.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5788.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5788.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5789.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5789.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5789.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5789.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5789.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5789.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5790.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5790.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5790.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5790.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5790.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5790.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5790.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5790.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5790.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5790.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5790.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5790.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5790.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5790.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5790.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5790.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5790.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5790.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5790.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5790.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5790.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5791.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5791.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5791.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5791.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5791.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5791.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5791.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5791.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5791.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5791.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5791.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5791.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5791.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5791.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5791.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5791.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5791.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5791.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5791.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5791.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5791.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5791.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5791.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5791.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5792.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5792.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5792.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5792.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5792.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5792.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5792.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5793.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5793.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5793.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5793.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5794.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5794.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5794.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5794.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5794.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5794.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5794.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5794.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5794.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5794.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5794.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5794.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5794.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5794.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5794.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5794.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5794.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5794.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5794.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5794.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5794.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5794.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5795.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5795.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5795.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5795.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5796.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5796.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5796.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5796.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5796.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5796.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5796.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5796.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5796.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5796.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5796.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5796.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5796.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5796.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5796.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5796.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5796.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5796.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5796.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5796.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5796.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5796.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5796.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5796.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5796.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5796.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5796.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5796.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5796.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5796.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5797.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5797.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5797.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5797.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5798.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5798.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5798.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5798.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5798.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5798.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5798.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5798.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5798.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5798.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5798.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5798.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5798.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5798.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5798.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5798.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5798.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5798.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5798.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5798.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5798.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5798.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5798.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5798.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5798.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5798.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5798.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5798.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5798.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5798.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5798.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5798.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5798.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5798.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5798.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5798.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5798.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5798.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5799.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5799.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5799.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5799.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5800.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5800.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5800.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5800.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5800.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5800.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5800.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5800.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5800.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5800.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5800.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5800.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5800.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5800.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5800.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5800.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5800.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5800.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5800.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5800.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5800.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5800.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5800.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5800.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5800.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5800.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5800.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5800.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5800.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5800.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5800.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5800.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5800.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5800.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5800.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5800.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5800.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5800.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5800.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5800.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5800.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5801.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5801.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5801.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5801.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5801.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5801.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5801.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5801.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5801.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5801.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5801.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5801.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5801.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5801.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5801.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5801.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5801.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5801.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5801.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5801.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5801.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5802.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5802.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5802.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5802.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5802.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5802.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5802.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5802.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5802.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5802.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5802.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5802.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5802.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5802.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5802.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5802.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5802.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5802.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5802.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5802.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5802.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5802.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5803.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5803.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5803.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5803.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5803.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5803.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5803.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5803.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5803.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5803.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5803.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5803.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5803.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5803.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5803.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5803.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5803.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5803.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5803.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5803.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5803.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5803.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5803.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5803.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5803.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5803.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5803.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48656c0] >[ 5803.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48656c0] width 1920 pitch 7680 (/4 1920) >[ 5803.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5803.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5803.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48656c0] >[ 5803.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48656c0] width 1920 pitch 7680 (/4 1920) >[ 5803.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5803.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5803.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5803.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5803.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5803.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5803.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5803.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5804.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5804.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5804.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5804.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5804.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5804.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5804.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5804.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5804.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5804.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5804.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5804.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5804.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5804.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5804.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5804.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5804.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5804.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5804.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5804.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5804.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48656c0] >[ 5804.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48656c0] width 1920 pitch 7680 (/4 1920) >[ 5804.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5804.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5804.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48656c0] >[ 5804.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48656c0] width 1920 pitch 7680 (/4 1920) >[ 5804.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5804.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5804.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5804.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5804.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5804.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5804.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5804.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5804.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5804.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5804.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5804.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5804.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5804.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5805.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5805.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5805.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5805.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5806.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5806.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5806.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5806.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5806.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5806.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5806.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5806.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5806.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5806.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5806.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5806.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5806.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5806.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5806.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5806.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5806.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5806.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5806.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5806.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5806.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5806.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5806.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5806.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5806.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5806.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5806.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5806.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5806.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5806.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5807.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5807.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5807.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5807.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5808.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5808.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5808.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5808.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5809.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5809.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5809.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5809.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5809.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5809.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5809.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5809.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5809.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5809.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5809.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5809.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5809.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5810.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5810.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5810.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5810.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5811.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5811.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5811.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5811.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4866760] >[ 5811.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4866760] width 1920 pitch 7680 (/4 1920) >[ 5811.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5811.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5811.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5811.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5811.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5811.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5811.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5811.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5811.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5811.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5811.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5811.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5811.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5811.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5812.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5812.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5812.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5812.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5812.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5812.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5812.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5812.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5812.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5812.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5812.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5812.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5812.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5812.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5812.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5812.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5812.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5812.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5812.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5812.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5812.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5812.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5812.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5812.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5812.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5812.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5812.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5812.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5812.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5812.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5812.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5812.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5813.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5813.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5813.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5813.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5813.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5813.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5813.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5813.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5813.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5813.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5813.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5813.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5813.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5813.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5813.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5813.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5813.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5813.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5813.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5813.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5813.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5813.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5813.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5813.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5813.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5813.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5813.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5813.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5813.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5814.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5814.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5814.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5814.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5814.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5814.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5815.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5815.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5815.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5815.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5815.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5815.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5815.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5815.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5815.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5815.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5815.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5815.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5815.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5815.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5815.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5815.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5815.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5815.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5815.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5815.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5815.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5815.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5815.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5815.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5815.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5815.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5815.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5815.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5815.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5815.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5815.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5815.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5815.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5815.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5816.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5816.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5816.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5816.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5816.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5816.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5816.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5816.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5816.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5816.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5816.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5816.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5816.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5816.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5816.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5816.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5816.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5816.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5816.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5816.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5816.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5816.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5816.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5816.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5817.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5817.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5817.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5817.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5817.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5817.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5817.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5817.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5817.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5817.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5817.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5817.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5817.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5817.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5817.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5818.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5818.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5818.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5818.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5818.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5818.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5818.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5818.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5818.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5818.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5818.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5818.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5818.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5818.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5818.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5818.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5818.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5818.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5818.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5818.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5818.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5818.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5818.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5818.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5818.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5818.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5818.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5818.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5819.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5819.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5819.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5819.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5819.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5819.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5819.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5819.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5819.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5819.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5819.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5819.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5819.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5819.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5819.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5819.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5819.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5819.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5819.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5819.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5819.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5819.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5819.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5819.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5819.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5819.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5819.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5819.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5819.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5819.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5819.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5819.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5819.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5819.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5819.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5819.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5819.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5820.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5820.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5820.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5820.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5820.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5820.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5820.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5820.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5820.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5820.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5820.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5820.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5820.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5820.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5820.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5820.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5820.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5820.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5820.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5820.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5820.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5821.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5821.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5821.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5821.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5821.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5821.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5821.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5821.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5821.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5821.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5821.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5821.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5821.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5821.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5821.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5821.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5821.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5821.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5822.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5822.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5822.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5822.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5822.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5822.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5822.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5822.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5822.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5822.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5822.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5822.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5822.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5822.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5822.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5822.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5822.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5822.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5822.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5822.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5822.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5822.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5822.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5822.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5822.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5822.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5822.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5822.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5823.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5823.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5823.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5823.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5823.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5823.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5824.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5824.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5824.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5824.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5825.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5825.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5825.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5825.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5825.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5825.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5825.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5825.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5825.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5825.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5825.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5825.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5825.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5825.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5825.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5825.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5825.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5825.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5825.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5825.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5825.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5826.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5826.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5826.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5826.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5827.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5827.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5827.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5827.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5827.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5827.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5827.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5827.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5827.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5827.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5827.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5827.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5827.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5827.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5827.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5827.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5827.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5827.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5827.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5827.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5827.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5827.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5827.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5827.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5827.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5827.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5827.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5827.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5827.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5827.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5827.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5827.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5827.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5827.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5827.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5827.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5827.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5827.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5827.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5827.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5827.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5827.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5827.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5827.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5827.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5827.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5828.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5828.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5828.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5828.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5828.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5828.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5828.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5828.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5828.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5828.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5828.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5828.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5828.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5828.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5828.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5828.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5828.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5828.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5828.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5828.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5828.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5828.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5828.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5828.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5828.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5828.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5828.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5828.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5828.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5828.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5828.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5828.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5828.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5828.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5828.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5828.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5828.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5828.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5828.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5828.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5828.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5828.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5828.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5828.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5828.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5828.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5828.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5829.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5829.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5829.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5829.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5829.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5829.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5829.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5829.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5830.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5830.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5830.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5830.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5831.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5831.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5831.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5831.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5832.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5832.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5832.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5832.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5832.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5832.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5832.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5832.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5832.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5832.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5832.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5832.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5832.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5832.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5832.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5832.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5832.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5832.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5832.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5832.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5832.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5832.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5832.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5832.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5833.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5833.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5833.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5833.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5834.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5834.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5834.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5834.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5834.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5834.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5834.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5834.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5834.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5834.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5834.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5834.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5834.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5834.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5834.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5834.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5834.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5834.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5834.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5834.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5834.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5834.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5834.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5834.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5834.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5834.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5834.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5834.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5834.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5834.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5834.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5834.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5835.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5835.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5835.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5835.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5835.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5835.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5835.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5835.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5835.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5835.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5835.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5835.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5835.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5835.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5835.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5836.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5836.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5836.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5836.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5836.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5836.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5836.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5836.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5836.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5836.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5836.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5836.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5836.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5836.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5836.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5836.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5836.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5836.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5836.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5836.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5836.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5836.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5836.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5836.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5836.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5836.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5836.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5836.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5836.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5836.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5836.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5836.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5836.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5836.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5836.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5836.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5836.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5836.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5836.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5836.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5837.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5837.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5837.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5837.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5837.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5837.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5837.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5837.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5837.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5837.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5837.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5837.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5837.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5837.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5837.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5837.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5837.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5837.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5837.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5837.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5837.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5837.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5837.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5837.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5837.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5837.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5837.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5837.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5837.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5837.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5837.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5837.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5837.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5837.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5837.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5837.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5837.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5837.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5837.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5837.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5838.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5838.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5838.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5838.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5838.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5838.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5838.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5838.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5838.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5838.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5838.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5838.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5838.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5838.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5838.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5838.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5838.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5838.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5838.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5838.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5838.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5838.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5839.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5839.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5839.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5839.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5840.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5840.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5840.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5840.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5840.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5840.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5840.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5840.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5840.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5840.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5840.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5840.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5840.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5840.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5840.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5840.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5840.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5840.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5840.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5840.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5840.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5840.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5841.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5841.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5841.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5841.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5841.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5841.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5842.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5842.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5842.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5842.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5842.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5842.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5842.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5842.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5842.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5842.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5842.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5842.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5842.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5842.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5842.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5842.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5842.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5842.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5842.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5842.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5842.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5843.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5843.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5843.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5843.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5844.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5844.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5844.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5844.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5844.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5844.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5844.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5844.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5844.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5844.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5844.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5844.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5844.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5844.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5844.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5844.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5844.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5844.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5844.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5844.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5844.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5845.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5845.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5845.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5845.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5845.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5845.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5845.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5845.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5845.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5845.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5845.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5845.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5845.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5845.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5845.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5845.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5845.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5845.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5845.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5845.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5845.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5845.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5845.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5845.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5846.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5846.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5846.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5846.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5846.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5846.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5846.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5846.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5846.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5846.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5846.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5846.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5846.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5846.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5846.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5846.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5846.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5846.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5846.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5846.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5846.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5847.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5847.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5847.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5847.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5847.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5847.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5847.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5847.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5847.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5847.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5847.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5847.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5847.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5847.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5847.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5847.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5847.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5847.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5847.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5847.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5847.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5847.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5848.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5848.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5848.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5848.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5848.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5848.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5848.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5848.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5848.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5848.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5848.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5848.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5848.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5848.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5848.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5848.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5848.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5848.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5848.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5848.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5848.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5848.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5848.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5848.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5848.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5848.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5848.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5848.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5848.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5848.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5848.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5848.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5848.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5848.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5848.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5848.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5848.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5848.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5848.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5848.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5848.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5849.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5849.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5849.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5849.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5849.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5849.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5849.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5849.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5849.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5849.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5849.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5849.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5849.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5849.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5849.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5849.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5849.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5849.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5849.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5849.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5849.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5849.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5849.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5849.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5850.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5850.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5850.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5850.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5850.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5850.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5850.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5850.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5850.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5850.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5850.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5850.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5850.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5850.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5850.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5850.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5850.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5850.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5850.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5850.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5850.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5850.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5850.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5850.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5850.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5850.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5850.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5850.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5850.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5850.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5850.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5850.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5850.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5850.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5850.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5850.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5850.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5850.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5850.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5850.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5851.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5851.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5851.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5851.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5851.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5851.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5851.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5851.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5851.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5851.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5851.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5851.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5851.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5851.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5851.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5851.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5851.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5851.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5851.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5851.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5851.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5851.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5851.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5851.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5851.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5851.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5851.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5851.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5851.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5851.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5851.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5851.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5851.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5851.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5851.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5851.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5851.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5851.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5852.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5852.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5852.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5852.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5852.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5852.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5852.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5852.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5852.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5852.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5852.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5852.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5852.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5852.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5852.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5852.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5852.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5852.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5852.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5852.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5852.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5852.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5853.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5853.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5853.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5853.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5853.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5854.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5854.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5854.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5854.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5854.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5854.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5854.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5854.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5854.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5854.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5854.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5854.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5854.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5854.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5854.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5854.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5854.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5854.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5854.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5854.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5854.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5855.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5855.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5855.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5855.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5855.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5855.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5855.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5855.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5855.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5855.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5855.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5855.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5855.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5855.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5855.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5855.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5855.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5855.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5855.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5855.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5855.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5855.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5855.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5856.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5856.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5856.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5856.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5856.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5856.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5856.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5856.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5856.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5856.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5856.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5856.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5856.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5856.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5856.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5856.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5856.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5856.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5856.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5856.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5856.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5856.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5856.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5856.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5856.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5856.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5856.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5856.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5856.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5856.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5856.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5856.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5856.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5856.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5856.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5856.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5856.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5856.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5856.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5856.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5857.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5857.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5857.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5857.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5858.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5858.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5858.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5858.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5858.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5858.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5858.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5858.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5858.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5858.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5858.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5858.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5858.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5858.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5858.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5858.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5858.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5858.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5858.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5858.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5858.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5858.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5859.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5859.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5859.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5859.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5859.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5859.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5859.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5859.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5859.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5859.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5859.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5859.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5859.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5859.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5859.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5859.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5859.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5859.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5859.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5859.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5859.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5859.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5860.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5860.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5860.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5860.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5861.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5861.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5861.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5861.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5861.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5861.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5861.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5861.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5861.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5861.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5861.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5861.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5861.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5861.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5861.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5861.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5861.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5861.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5861.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5861.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5861.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5862.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5862.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5862.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5862.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5862.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5862.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5862.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5862.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5862.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5862.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5862.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5862.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5862.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5862.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5862.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5862.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5862.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5862.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5862.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5862.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5862.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5862.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5862.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5862.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5862.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5862.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5862.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5862.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5862.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5862.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5862.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5862.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5862.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5862.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5862.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5862.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5862.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5862.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5863.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5863.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5863.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5863.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5863.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5863.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5863.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5863.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5863.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5863.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5863.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5863.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5863.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5863.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5863.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5863.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5863.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5863.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5863.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5863.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5863.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5864.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5864.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5864.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5864.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5864.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5864.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5864.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5864.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5864.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5864.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5864.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5864.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5864.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5864.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5864.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5864.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5864.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5864.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5864.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5864.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5864.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5864.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5864.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5864.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5864.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5864.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5864.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5864.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5864.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5865.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5865.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5865.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5865.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5865.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5865.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5865.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5865.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5865.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5865.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5865.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5865.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5865.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5865.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5865.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5865.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5865.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5865.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5865.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5865.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5865.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5865.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5865.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5865.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5865.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5865.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5865.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5865.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5865.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5865.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5865.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5865.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5865.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5865.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5865.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5865.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5865.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5865.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5865.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5866.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5866.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5866.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5866.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5866.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5866.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5866.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5866.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5866.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5866.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5866.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5866.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5866.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5866.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5866.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5866.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5866.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5866.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5866.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5866.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5866.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5866.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5866.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5866.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5866.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5866.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5866.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5866.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5866.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5866.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5866.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5866.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5866.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5866.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5866.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5866.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5867.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5867.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5867.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5867.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5867.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5867.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5867.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5867.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5867.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5867.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5867.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5867.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5867.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5867.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5867.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5867.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5867.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5867.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5867.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5867.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5867.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5867.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5867.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5867.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5867.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5867.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5867.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5867.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5867.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5867.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5868.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5868.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5868.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5868.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5868.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5868.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5868.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5868.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5868.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5868.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5868.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5868.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5868.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5868.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5868.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5868.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5868.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5868.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5868.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5868.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5869.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5869.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5869.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5869.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5869.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5869.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5869.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5869.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5869.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5869.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5869.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5869.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5869.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5869.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5869.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5869.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5869.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5869.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5869.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5869.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5869.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5869.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5869.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5869.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5869.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5869.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5869.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5869.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5869.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5869.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5869.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5869.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5869.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5869.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5869.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5869.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5869.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5870.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5870.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5870.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5870.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5870.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5870.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5870.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5870.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5870.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5870.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5870.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5870.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5870.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5870.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5870.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5870.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5870.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5870.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5870.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5870.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5871.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5871.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5871.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5871.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5871.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5871.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5871.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5871.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5871.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5871.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5871.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5871.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5871.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5871.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5871.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5871.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5871.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5871.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5871.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5871.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5871.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5871.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5871.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5871.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5871.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5871.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5871.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5871.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5871.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5871.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5871.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5872.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5872.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5872.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5872.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5872.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5872.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5872.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5872.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5872.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5872.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5872.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5872.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5872.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5872.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5872.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5872.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5872.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5872.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5872.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5872.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5872.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5872.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5872.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5873.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5873.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5873.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5873.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5873.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5873.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5873.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5873.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5873.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5874.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5874.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5874.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5874.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5874.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5874.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5874.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5874.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5874.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5875.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5875.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5875.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5875.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5875.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5875.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5875.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5875.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5875.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5875.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5875.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5875.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5875.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5875.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5875.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5875.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5875.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5875.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5875.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5875.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5875.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5875.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5875.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5875.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5875.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5875.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5875.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5875.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5875.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5875.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5876.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5876.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5876.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5876.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5877.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5877.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5877.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5877.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5877.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5877.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5877.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5877.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5877.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5877.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5877.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5877.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5878.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5878.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5878.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5878.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5878.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5878.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5878.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5878.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5878.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5878.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5878.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5878.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5878.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5878.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5878.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5878.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5878.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5878.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5878.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5878.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5878.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5879.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5879.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5879.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5879.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5879.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5879.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5879.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5879.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5879.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5879.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5880.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5880.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5880.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5880.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5880.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5880.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5880.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5880.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5880.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5880.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5880.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5880.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5880.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5881.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5881.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5881.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5881.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5881.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5881.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5881.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5881.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5881.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5881.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5881.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5881.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5881.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5881.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5881.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5881.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5881.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5881.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5881.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5881.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5881.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5881.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5881.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5882.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5882.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5882.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5882.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5882.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5882.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5882.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5882.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5882.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5882.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5882.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5882.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5882.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5882.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5882.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5882.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5882.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5882.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5882.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5882.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5882.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5883.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5883.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5883.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5883.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5884.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5884.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5884.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5884.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5884.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5885.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5885.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5885.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5885.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5885.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5885.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5885.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5885.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5885.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5885.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5885.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5885.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5885.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5885.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5885.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5886.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5886.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5886.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5886.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5886.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5886.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5886.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5886.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5887.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5887.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5887.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5887.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5887.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5887.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5887.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5887.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5887.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5887.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5887.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5887.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5887.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5887.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5887.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5887.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5887.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5887.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5887.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5887.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5887.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5887.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5887.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5887.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5887.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5887.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5887.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5888.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5888.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5888.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5888.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5888.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5888.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5888.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5888.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5888.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5888.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5888.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5888.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5888.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5888.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5888.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5888.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5888.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5888.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5888.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5888.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5888.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5888.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5888.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5888.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5888.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5889.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5889.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5889.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5889.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5889.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5889.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5889.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5889.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5889.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5889.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5889.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5889.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5889.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5889.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5889.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5889.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5889.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5889.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5889.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5889.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5889.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5889.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5889.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5889.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5889.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5889.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5889.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5889.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5889.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5889.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5889.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5889.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5890.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5890.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5890.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5890.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5890.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5890.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5890.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5890.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5890.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5890.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5890.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5890.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5890.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5890.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5890.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5890.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5890.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5890.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5890.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5890.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5890.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5890.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5890.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5890.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5890.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5890.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5890.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5890.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5890.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5890.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5890.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5890.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5890.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5890.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5890.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5890.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5890.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5890.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5890.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5890.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5890.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5890.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5890.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5890.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5890.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5890.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5891.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5891.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5891.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5891.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5892.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5892.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5892.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5892.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5892.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5892.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5892.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5892.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5892.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5892.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5892.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5892.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5892.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5892.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5892.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5892.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5892.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5892.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5892.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5892.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5892.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5892.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5892.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5892.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5892.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5893.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5893.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5893.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5893.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5893.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5893.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5893.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5893.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5893.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5893.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5893.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5893.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5893.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5893.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5893.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5893.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5893.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5893.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5893.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5893.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5893.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5893.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5893.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5893.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5894.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5894.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5894.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5894.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5894.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5894.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5894.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5894.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5895.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5895.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5895.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5895.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5895.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5895.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5895.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5895.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5895.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5895.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5895.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5895.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5895.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5895.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5895.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5895.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5895.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5895.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5895.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5895.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5895.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5895.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5895.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5895.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5896.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5896.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5896.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5896.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5896.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5896.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5896.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5896.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5896.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5896.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5896.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5896.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5896.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5896.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5896.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5896.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5896.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5896.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5896.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5896.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5896.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5896.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5896.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5897.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5897.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5897.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5897.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5897.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5897.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5898.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5898.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5898.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5898.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5898.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5898.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5898.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5898.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5898.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5898.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5898.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5898.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5898.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5898.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5898.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5898.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5898.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5898.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5898.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5898.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5898.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5898.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5898.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5898.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5898.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5898.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5898.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5898.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5898.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5898.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5898.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5898.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5898.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5898.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5898.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5898.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5898.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5898.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5898.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5898.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5898.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5898.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5898.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5899.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5899.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5899.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5899.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5899.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5899.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5899.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5899.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5899.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5899.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5899.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5899.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5899.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5899.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5899.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5899.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5899.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5899.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5899.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5899.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5899.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5899.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5899.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5899.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5900.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5900.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5900.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5900.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5901.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5901.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5901.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5901.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5901.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5901.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5901.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5901.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5901.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5901.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5901.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5901.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5901.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5901.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5901.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5901.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5901.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5901.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5901.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5901.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5901.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5901.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5901.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5901.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5901.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5901.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5902.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5902.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5902.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5902.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5902.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5902.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5902.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5902.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5902.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5902.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5902.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5902.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5902.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5902.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5902.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5902.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5902.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5902.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5902.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5902.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5902.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5902.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5902.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5902.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5902.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5902.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5902.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5902.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5902.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5902.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5902.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5902.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5902.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5902.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5902.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5902.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5902.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5902.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5902.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5902.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5902.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5902.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5903.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5903.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5903.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5903.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5903.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5903.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5903.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5903.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5903.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5903.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5903.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5903.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5903.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5903.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5903.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5904.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5904.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5904.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5904.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5904.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5904.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5904.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5904.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5904.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5904.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5904.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5904.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5904.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5904.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5904.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5904.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5904.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5904.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5904.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5904.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5904.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5904.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5905.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5905.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5905.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5905.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5905.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5905.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5905.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5905.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5905.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5905.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5905.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5905.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5905.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5905.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5905.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5905.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5905.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5905.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5905.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5905.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5905.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5905.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5905.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5906.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5906.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5906.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5906.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5907.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5907.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5907.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5907.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5907.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5907.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5907.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5907.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5907.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5907.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5907.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5907.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5907.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5907.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5907.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5907.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5907.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5907.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5907.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5907.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5907.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5907.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5907.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5907.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5908.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5908.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5908.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5908.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5909.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5909.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5909.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5909.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5910.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5910.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5910.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5910.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5910.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5910.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5910.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5910.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5910.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5910.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5910.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5910.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5910.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5910.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5910.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5910.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5910.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5910.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5910.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5910.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5910.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5910.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5911.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5911.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5911.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5911.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5912.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5912.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5912.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5912.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5912.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5912.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5912.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5912.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5912.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5912.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5912.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5912.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5912.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5912.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5912.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5912.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5912.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5912.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5912.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5912.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5912.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5913.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5913.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5913.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5913.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5914.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5914.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5914.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5914.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5914.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5914.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5914.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5914.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5914.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5914.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5914.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5914.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5914.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5914.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5914.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5914.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5914.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5914.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5914.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5914.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5914.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5914.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5914.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5914.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5914.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5914.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5914.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5914.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5914.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5914.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5914.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5914.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5914.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5914.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5914.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5914.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5914.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5914.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5915.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5915.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5915.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5915.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5915.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5915.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5915.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5915.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5915.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5915.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5915.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5915.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5915.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5915.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5915.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5915.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5915.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5915.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5915.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5915.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5915.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5916.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5916.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5916.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5916.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5916.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5916.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5916.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5916.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5916.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5916.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5916.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5916.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5916.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5916.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5916.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5916.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5916.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5916.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5916.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5916.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5916.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5916.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5916.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5916.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5916.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5916.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5916.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5916.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5916.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5916.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5916.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5916.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5916.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5916.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5916.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5916.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5916.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5916.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5916.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5917.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5917.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5917.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5917.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5917.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5917.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5917.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5917.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5917.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5917.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5917.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5917.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5917.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5917.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5917.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5917.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5917.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5917.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5917.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5917.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5917.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5917.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5917.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5917.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5918.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5918.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5918.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5918.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5918.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5918.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5918.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5918.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5918.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5918.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5918.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5918.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5918.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5918.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5918.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5918.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5918.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5918.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5918.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5918.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5918.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5919.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5919.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5919.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5919.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5919.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5919.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5919.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5919.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5919.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5919.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5919.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5919.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5919.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5919.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5919.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5919.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5919.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5919.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5919.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5919.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5919.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5920.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5920.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5920.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5920.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5920.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5920.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5920.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5920.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5920.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5920.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5920.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5920.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5920.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5920.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5920.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5920.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5920.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5920.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5920.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5920.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5920.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5920.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5920.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5920.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5920.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5920.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5920.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5920.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5920.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5920.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5920.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5920.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5920.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5920.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5920.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5920.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5920.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5920.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5920.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5920.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5921.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5921.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5921.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5921.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5921.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5921.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5921.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5921.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5921.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5921.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5921.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5921.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5921.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5921.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5921.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5921.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5921.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5921.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5921.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5921.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5921.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5921.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5921.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5921.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5921.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5921.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5921.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5921.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5921.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5921.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5921.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5921.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5922.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5922.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5922.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5922.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5922.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5922.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5922.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5922.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5922.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5922.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5922.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5922.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5922.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5922.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5922.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5922.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5922.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5922.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5922.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5922.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5923.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5923.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5923.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5923.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5923.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5923.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5923.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5923.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5923.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5923.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5923.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5923.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5923.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5923.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5923.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5923.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5923.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5923.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5923.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5923.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5923.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5924.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5924.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5924.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5924.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5924.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5924.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5924.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5924.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5924.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5924.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5924.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5924.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5924.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5924.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5924.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5924.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5924.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5924.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5924.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5924.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5924.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5924.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5924.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5924.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5924.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5924.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5924.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5924.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5924.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5924.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5924.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5924.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5924.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5925.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5925.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5925.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5925.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5925.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5925.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5925.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5925.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5925.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5925.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5925.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5925.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5925.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5925.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5925.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5925.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5925.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5925.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5925.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5925.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5925.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5925.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5925.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5925.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5925.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5925.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5925.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5925.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5925.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5925.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5925.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5925.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5925.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5925.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5925.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5925.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5925.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5925.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5925.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5925.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5925.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5926.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5926.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5926.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5926.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5926.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5926.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5926.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5926.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5926.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5926.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5926.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5926.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5926.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5926.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5926.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5926.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5926.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5926.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5926.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5926.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5926.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5926.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5927.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5927.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5927.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5927.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5927.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5927.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5927.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5927.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5927.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5927.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5927.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5927.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5927.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5927.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5927.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5927.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5927.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5927.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5927.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5927.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5927.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5927.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5927.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5927.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5927.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5927.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5927.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5927.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5927.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5927.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5927.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5927.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5927.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5927.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5927.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5927.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5927.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5927.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5927.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5927.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5927.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5927.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5927.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5928.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5928.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5928.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5928.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5929.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5929.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5929.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5929.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5929.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5929.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5929.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5929.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5929.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5929.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5929.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5929.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5929.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5929.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5929.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5929.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5929.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5929.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5929.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5929.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5929.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5929.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5929.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5929.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5929.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5929.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5929.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5930.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5930.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5930.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5930.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5930.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5930.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5931.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5931.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5931.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5931.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5931.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5931.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5931.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5931.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5931.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5931.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5931.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5931.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5931.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5931.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5931.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5931.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5931.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5931.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5931.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5931.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5931.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5931.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5931.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5931.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5931.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5931.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5931.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5931.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5931.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5931.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5931.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5931.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5931.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5931.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5931.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5931.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5931.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5931.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5931.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5931.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5931.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5931.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5931.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5932.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5932.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5932.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5932.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5932.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5932.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5933.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5933.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5933.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5933.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5933.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5933.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5933.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5933.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5933.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5933.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5933.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5933.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5933.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5933.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5933.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5933.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5933.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5933.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5933.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5933.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5933.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5933.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5933.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5933.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5933.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5933.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5934.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5934.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5934.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5934.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5934.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5934.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5934.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5934.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5934.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5934.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5934.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5934.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5934.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5934.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5934.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5934.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5934.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5934.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5934.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5934.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5934.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5934.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5934.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5934.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5934.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5934.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5935.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5935.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5935.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5935.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5935.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5935.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5935.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5935.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5935.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5935.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5935.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5935.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5935.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5935.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5935.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5935.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5935.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5935.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5935.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5935.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5935.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5935.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5935.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5935.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5935.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5935.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5935.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5935.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5935.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5935.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5935.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5935.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5935.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5935.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5935.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5935.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5935.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5935.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5935.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5935.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5935.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5935.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5935.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5935.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5936.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5936.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5936.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5936.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5936.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5936.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5936.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5936.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5936.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5936.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5936.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5936.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5936.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5936.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5936.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5936.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5936.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5936.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5936.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5936.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5936.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5936.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5936.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5936.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5936.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5936.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5936.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5937.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5937.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5937.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5937.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5937.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5937.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5937.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5937.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5937.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5937.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5937.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5937.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5937.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5937.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5937.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5937.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5937.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5937.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5937.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5937.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5937.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5937.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5937.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5937.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5937.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5937.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5937.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5937.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5937.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5937.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5937.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5937.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5937.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5937.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5937.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5937.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5937.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5937.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5937.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5937.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5937.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5937.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5937.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5937.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5938.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5938.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5938.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5938.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5939.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5939.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5939.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5939.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5940.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5940.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5940.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5940.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5940.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5940.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5940.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5940.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5940.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5940.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5940.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5940.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5940.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5940.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5940.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5940.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5940.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5940.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5940.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5940.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5940.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5940.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5940.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5940.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5940.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5940.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5940.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5940.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5940.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5940.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5940.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5940.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5940.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5940.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5940.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5940.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5940.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5940.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5941.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5941.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5941.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5941.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5941.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5941.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5941.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5941.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5941.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5941.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5941.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5941.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5941.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5941.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5941.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5942.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5942.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5942.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5942.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5942.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5942.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5942.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5942.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5942.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5942.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5942.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5943.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5943.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5943.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5943.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5943.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5943.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5943.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5944.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5944.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5944.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5944.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5944.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5944.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5944.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5944.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5944.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5944.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5944.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5944.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5944.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5944.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5944.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5944.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5944.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5944.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5944.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5944.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5944.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5944.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5944.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5944.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5944.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5944.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5944.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5944.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5944.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5944.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5944.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5944.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5944.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5945.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5945.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5945.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5945.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5946.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5946.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5946.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5946.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5947.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5947.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5947.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5947.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5948.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5948.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5948.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5948.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5948.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5948.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5948.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5948.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5948.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5948.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5948.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5948.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5948.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5948.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5948.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5948.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5948.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5948.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5948.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5948.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5948.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5948.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5948.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5948.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5948.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5948.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5948.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5948.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5948.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5948.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5948.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5949.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5949.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5949.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5949.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5949.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5949.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5949.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5949.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5949.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5949.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5949.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5949.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5949.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5949.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5949.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5949.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5949.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5949.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5949.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5949.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5949.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5949.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5949.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5949.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5949.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5949.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5949.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5949.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5950.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5950.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5950.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5950.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5950.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5950.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5950.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5950.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5950.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5950.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5950.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5950.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5950.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5950.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5950.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5950.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5950.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5950.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5951.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5951.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5951.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5951.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5951.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5951.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5951.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5951.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5951.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5951.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5951.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5952.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5952.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5952.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5952.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5952.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5953.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5953.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5953.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5953.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5953.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5953.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5953.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5953.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5953.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5953.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5953.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5953.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5953.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5953.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5953.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5953.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5954.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5954.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5954.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5954.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5954.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5954.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5954.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5954.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5954.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5954.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5954.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5954.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5954.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5954.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5954.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5954.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5954.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5954.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5954.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5954.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5954.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5954.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5954.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5954.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5954.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5954.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5954.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5954.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5954.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5954.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5954.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5954.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5954.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5954.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5954.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5954.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5954.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5954.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5954.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5954.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5954.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5954.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5955.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5955.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5955.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5955.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5956.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5956.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5956.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5956.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5956.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5956.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5956.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5956.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5956.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5956.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5956.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5956.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5956.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5956.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5956.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5956.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5957.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5957.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5957.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5957.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5958.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5958.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5958.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5958.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5958.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5958.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5958.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5958.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5958.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5958.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5958.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5958.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5958.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5958.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5958.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5958.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5958.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5958.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5958.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5958.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5958.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5958.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5958.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5958.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5958.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5958.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5958.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5958.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5958.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5958.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5958.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5958.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5958.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5958.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5958.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5958.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5958.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5958.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5958.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5958.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5959.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5959.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5959.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5959.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5959.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5959.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5959.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5959.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5959.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5959.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5959.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5959.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5959.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5959.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5959.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5959.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5959.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5959.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5959.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5959.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5959.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5959.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5959.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5959.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5959.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5959.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5959.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5959.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5959.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5959.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5959.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5959.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5959.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5959.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5959.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5959.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5959.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5959.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5959.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5959.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5959.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5959.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5959.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5959.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5959.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5959.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5960.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5960.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5960.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5960.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5960.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5960.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5960.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5960.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5960.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5960.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5960.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5960.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5960.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5960.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5960.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5960.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5960.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5960.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5960.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5960.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5960.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5960.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5960.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5960.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5960.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5960.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5960.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5960.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5961.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5961.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5961.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5961.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5961.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5961.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5961.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5961.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5961.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5961.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5961.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5961.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5961.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5961.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5961.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5961.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5961.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5961.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5961.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5961.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5961.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5961.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5961.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5961.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5961.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5961.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5962.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5962.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5962.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5962.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5962.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5962.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5963.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5963.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5963.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5963.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5964.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5964.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5964.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5964.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5964.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5964.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5964.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5964.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5964.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5964.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5964.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5964.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5964.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5964.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5964.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5964.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5964.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5964.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5964.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5964.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5964.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5965.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5965.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5965.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5965.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5966.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5966.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5966.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5966.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5966.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5966.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5966.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5966.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5966.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5966.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5966.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5966.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5966.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5966.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5966.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5967.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5967.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5967.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5967.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5967.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5967.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5967.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5967.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5967.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5967.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5967.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5967.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5967.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5967.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5967.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5967.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5967.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5967.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5967.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5967.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5967.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5967.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5967.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5968.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5968.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5968.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5968.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5968.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5968.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5968.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5968.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5968.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5968.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5968.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5968.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5968.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5968.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5968.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5968.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5968.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5968.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5968.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5968.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5968.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5968.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5968.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5968.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5968.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5968.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5968.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5968.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5968.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5968.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5968.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5968.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5968.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5968.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5968.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5968.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5968.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5968.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5968.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5968.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5968.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5968.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5969.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5969.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5969.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5969.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5969.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5969.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5969.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5969.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5969.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5969.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5969.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5969.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5969.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5969.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5969.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5969.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5969.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5969.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5969.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5969.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5969.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5969.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5969.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5969.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5969.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5969.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5969.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5969.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5969.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5969.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5969.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5969.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5970.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5970.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5970.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5970.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5970.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5970.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5970.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5971.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5971.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5971.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5971.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5971.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5971.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5971.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5971.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5971.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5971.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5971.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5971.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5971.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5971.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5971.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5971.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5971.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5971.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5971.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5971.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5971.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5971.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5972.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5972.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5972.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5972.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5972.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5972.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5972.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5972.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5972.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5972.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5972.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5972.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5972.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5972.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5972.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5972.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5972.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5972.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5972.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5972.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5972.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5972.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5973.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5973.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5973.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5973.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5973.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5973.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5973.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5973.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5973.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5974.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5974.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5974.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5974.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5974.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5974.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5974.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5974.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5974.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5974.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5974.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5974.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5974.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5974.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5974.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5974.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5974.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5974.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5974.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5974.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5974.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5974.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5974.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5974.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5974.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5974.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5974.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5974.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5974.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5974.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5974.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5974.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5975.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5975.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5975.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5975.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5975.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5975.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5975.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5975.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5975.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5975.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5975.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5975.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5975.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5975.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5975.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5975.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5975.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5975.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5975.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5975.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5975.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5975.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5975.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5975.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5976.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5976.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5976.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5976.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5977.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5977.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5977.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5977.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5977.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5977.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5977.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5977.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5977.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5977.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5977.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5977.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5977.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5977.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5977.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5977.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5977.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5977.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5977.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5977.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5977.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5977.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5977.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5978.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5978.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5978.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5978.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5979.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5979.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5979.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5979.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5980.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5980.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5980.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5980.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5981.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5981.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5981.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5981.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5981.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5981.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5981.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5981.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5981.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5981.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5981.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5981.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5981.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5981.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5981.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5981.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5981.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5981.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5981.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5981.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5981.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5981.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5981.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5981.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5981.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5981.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5982.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5982.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5982.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5982.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5982.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5982.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5982.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5982.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5982.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5982.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5982.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5982.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5982.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5982.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5982.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5982.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5982.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5982.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5982.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5982.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5982.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5982.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5982.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5982.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5982.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5983.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5983.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5983.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5983.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5983.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5983.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5983.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5983.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5983.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5983.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5983.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5983.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5983.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5983.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5983.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5983.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5983.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5983.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5983.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5983.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5983.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5983.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5983.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5983.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5983.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5983.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5983.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5983.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5983.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5983.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5983.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5983.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5983.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5983.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5983.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5983.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5983.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5983.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5983.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5984.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5984.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5984.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5984.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5985.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5985.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5985.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5985.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5986.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5986.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5986.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5986.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5986.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5986.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5986.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5986.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5986.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5986.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5986.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5986.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5986.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5986.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5986.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5986.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5986.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5986.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5986.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5986.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5986.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5986.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5986.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5986.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5987.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5987.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5987.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5987.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5987.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5987.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5988.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5988.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5988.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5988.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5988.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5988.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5988.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5988.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5988.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5988.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5988.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5988.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5988.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5988.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5988.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5988.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5988.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5988.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5988.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5988.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5988.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5988.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5988.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5988.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5989.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5989.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5989.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5989.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5989.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5989.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5989.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5989.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5989.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5989.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5989.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5989.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5989.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5989.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5989.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5989.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5989.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5989.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5989.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5989.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5989.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5989.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5989.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5989.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5989.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5989.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5989.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5989.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5989.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5989.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5989.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5989.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5989.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5989.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5989.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5989.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5989.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5989.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5989.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5990.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5990.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5990.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5990.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5990.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5990.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5990.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5990.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5990.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5990.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5990.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5990.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5990.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5990.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5990.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5990.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5990.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5990.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5990.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5990.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5990.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5990.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5990.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5990.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5990.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5990.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5990.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5990.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5990.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5990.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5990.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5990.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5990.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5990.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5990.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5990.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5990.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5990.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5990.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5991.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5991.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5991.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5991.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5991.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5991.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5991.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5991.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5991.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5991.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5991.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5991.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5991.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5991.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5991.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5991.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5991.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5991.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5991.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5991.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5991.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5991.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5991.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5991.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5991.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5991.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5991.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5991.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5991.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5991.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5991.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5991.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5991.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5991.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5991.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5991.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5991.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5991.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5991.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5991.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5992.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5992.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5992.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5992.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5992.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5992.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5992.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5992.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5992.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5992.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5992.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5992.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5992.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5992.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5992.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5992.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5992.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5992.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5992.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5992.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5992.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5992.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5992.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5992.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5992.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5992.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5992.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5992.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5992.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5992.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5992.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5992.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5992.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5992.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5992.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5992.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5992.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5992.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5992.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5992.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5993.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5993.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5993.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5993.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5993.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5993.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5993.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5993.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5993.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5993.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5993.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5993.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5993.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5993.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5993.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5993.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5993.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5993.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5993.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5993.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5993.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5993.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5993.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5993.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5993.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5993.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5993.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5993.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5993.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5993.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5993.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5993.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5993.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5994.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5994.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5994.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5994.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5994.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5994.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5994.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5994.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5994.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5994.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5994.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5994.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5994.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5994.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5994.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5994.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5994.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5994.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5994.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5994.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5994.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5994.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5994.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5994.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5995.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5995.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5995.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5995.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5995.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5995.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5995.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5995.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5995.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5995.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5995.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5995.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5995.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5995.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5995.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5995.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5995.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5995.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5995.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5995.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5995.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5995.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5995.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5995.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5996.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5996.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5996.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5996.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5996.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5996.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5997.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5997.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5997.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5997.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5997.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5997.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5997.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5997.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5997.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5997.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5997.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5997.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5997.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5997.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5997.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5997.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5997.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5997.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5997.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5997.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5997.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5997.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5998.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5998.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5998.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5998.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5998.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5998.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5998.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5998.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5998.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5998.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5998.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5998.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5998.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5998.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5998.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5998.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5998.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5998.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5998.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 5998.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 5998.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5998.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5998.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5998.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5998.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5998.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5998.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5998.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5998.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5998.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5998.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5998.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5998.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5998.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5998.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5998.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5998.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5998.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5998.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5998.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5999.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5999.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5999.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5999.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5999.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5999.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5999.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5999.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5999.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5999.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5999.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5999.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5999.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5999.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5999.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 5999.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 5999.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5999.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5999.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5999.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5999.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5999.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5999.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5999.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5999.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5999.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5999.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5999.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 5999.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 5999.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 5999.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 5999.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6000.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6000.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6000.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6000.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6000.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6000.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6000.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6000.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6000.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6000.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6000.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6000.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6000.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6000.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6000.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6000.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6000.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6000.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6000.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6000.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6000.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6000.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6001.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6001.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6001.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6001.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6001.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6001.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6001.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6001.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6001.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6001.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6001.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6001.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6001.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6001.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6001.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6001.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6001.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6001.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6001.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6001.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6001.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6001.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6001.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6001.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6001.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6001.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6001.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6001.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6001.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6001.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6001.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6001.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6001.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6001.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6001.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6001.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6001.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6001.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6002.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6002.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6002.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6002.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6002.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6002.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6002.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6002.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6002.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6002.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6002.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6002.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6002.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6002.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6002.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6002.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6002.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6002.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6002.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6002.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6002.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6002.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6002.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6002.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6003.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6003.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6003.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6003.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6003.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6003.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6003.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6003.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6003.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6003.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6003.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6003.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6003.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6003.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6003.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6003.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6003.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6003.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6003.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6003.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6003.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6004.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6004.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6004.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6004.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6004.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6004.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6004.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6004.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6004.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6004.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6004.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6004.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6004.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6004.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6004.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6004.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6004.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6004.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6004.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6004.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6004.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6004.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6004.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6004.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6004.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6004.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6004.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6004.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6004.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6004.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6004.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6004.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6004.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6004.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6004.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6004.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6004.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6004.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6004.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6004.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6004.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6004.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6005.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6005.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6005.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6005.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6005.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6005.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6005.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6005.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6005.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6005.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6005.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6005.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6005.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6005.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6005.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6005.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6005.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6005.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6005.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6005.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6005.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6005.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6005.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6005.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6005.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6005.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6005.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6005.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6005.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6005.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6005.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6005.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6005.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6005.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6006.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6006.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6006.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6006.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6006.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6006.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6006.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6006.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6006.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6006.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6006.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6006.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6006.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6007.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6007.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6007.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6007.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6008.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6008.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6008.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6008.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6008.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6008.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6008.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6008.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6008.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6008.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6008.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6008.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6008.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6008.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6008.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6008.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6008.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6008.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6008.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6008.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6008.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6008.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6008.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6008.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6008.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6008.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6008.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6008.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6008.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6008.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6008.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6008.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6008.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6008.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6008.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6009.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6009.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6009.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6009.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6009.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6009.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6009.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6009.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6009.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6009.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6009.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6009.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6009.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6009.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6010.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6010.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6010.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6010.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6010.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6011.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6011.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6011.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6011.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6011.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6011.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6011.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6011.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6011.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6011.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6011.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6011.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6011.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6011.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6011.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6011.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6011.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6011.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6011.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6011.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6011.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6011.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6011.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6011.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6011.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6011.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6011.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6011.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6011.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6011.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6012.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6012.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6012.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6012.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6012.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6012.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6012.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6012.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6012.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6012.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6012.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6012.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6012.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6012.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6012.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6012.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6012.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6012.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6012.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6012.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6012.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6012.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6012.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6012.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6012.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6012.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6012.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6012.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6012.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6012.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6012.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6012.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6013.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6013.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6013.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6013.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6013.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6013.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6014.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6014.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6014.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6014.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6014.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6014.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6014.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6014.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6014.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6014.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6014.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6014.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6014.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6014.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6014.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6014.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6014.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6014.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6014.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6014.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6014.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6014.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6014.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6014.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6014.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6014.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6014.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6014.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6014.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6014.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6015.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6015.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6015.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6015.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6015.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6015.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6015.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6015.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6015.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6015.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6015.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6015.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6015.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6015.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6015.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6015.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6015.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6015.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6015.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6015.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6015.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6015.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6015.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6015.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6015.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6015.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6015.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6015.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6016.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6016.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6016.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6016.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6016.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6016.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6016.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6016.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6016.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6016.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6016.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6016.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6016.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6016.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6016.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6016.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6016.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6016.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6016.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6016.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6016.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6016.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6016.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6016.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6016.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6016.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6017.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6017.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6017.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6017.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6017.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6017.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6017.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6017.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6017.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6017.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6017.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6017.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6017.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6017.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6017.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6017.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6017.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6017.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6017.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6017.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6017.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6017.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6017.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6017.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6018.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6018.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6018.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6018.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6018.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6018.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6018.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6018.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6018.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6018.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6019.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6019.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6019.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6019.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6019.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6019.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6019.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6019.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6019.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6019.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6019.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6019.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6019.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6019.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6019.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6019.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6019.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6019.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6019.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6019.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6019.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6019.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6019.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6019.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6019.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6019.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6019.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6019.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6019.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6019.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6019.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6019.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6019.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6019.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6019.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6019.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6019.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6019.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6019.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6019.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6019.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6019.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6019.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6019.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6019.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6019.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6019.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6019.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6019.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6020.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6020.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6020.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6020.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6021.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6021.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6021.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6021.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6021.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6021.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6021.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6021.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6021.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6021.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6021.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6021.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6021.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6021.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6021.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6021.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6021.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6021.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6021.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6021.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6021.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6021.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6021.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6021.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6021.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6022.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6022.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6022.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6022.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6022.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6022.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6022.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6022.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6022.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6022.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6022.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6022.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6022.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6022.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6022.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6022.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6022.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6022.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6022.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6022.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6022.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6022.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6022.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6022.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6022.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6022.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6023.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6023.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6023.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6023.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6023.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6023.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6023.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6023.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6023.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6024.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6024.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6024.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6024.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6024.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6024.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6024.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6024.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6024.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6024.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6024.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6024.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6024.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6024.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6024.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6024.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6024.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6024.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6024.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6024.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6024.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6024.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6024.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6024.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6025.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6025.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6025.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6025.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6025.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6025.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6025.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6025.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6025.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6025.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6025.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6025.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6025.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6025.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6025.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6025.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6025.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6025.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6025.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6025.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6025.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6025.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6025.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6025.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6025.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6025.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6025.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6025.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6026.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6026.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6026.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6026.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6026.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6026.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6026.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6026.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6026.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6026.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6026.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6026.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6026.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6026.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6026.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6026.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6026.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6026.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6026.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6026.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6026.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6026.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6026.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6026.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6026.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6026.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6027.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6027.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6027.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6027.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6027.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6027.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6027.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6028.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6028.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6028.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6028.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6028.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6028.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6028.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6028.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6028.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6028.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6028.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6028.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6028.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6028.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6028.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6028.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6028.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6028.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6028.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6028.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6028.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6028.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6028.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6028.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6028.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6028.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6029.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6029.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6029.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6029.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6029.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6029.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6029.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6029.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6029.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6029.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6029.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6029.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6029.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6029.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6029.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6029.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6029.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6029.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6029.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6029.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6029.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6029.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6029.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6029.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6029.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6029.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6029.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6029.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6029.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6029.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6029.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6029.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6029.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6029.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6029.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6029.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6029.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6029.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6029.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6029.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6029.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6029.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6030.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6030.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6030.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6030.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6030.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6030.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6030.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6030.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6030.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6030.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6030.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6030.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6030.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6030.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6030.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6030.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6030.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6030.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6030.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6030.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6030.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6030.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6030.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6030.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6030.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6031.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6031.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6031.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6031.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6031.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6031.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6031.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6031.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6031.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6031.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6031.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6031.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6031.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6031.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6031.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6031.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6031.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6031.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6031.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6031.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6031.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6031.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6031.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6031.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6031.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6031.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6031.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6031.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6031.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6031.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6031.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6031.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6031.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6031.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6031.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6031.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6031.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6031.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6031.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6031.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6031.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6031.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6031.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6032.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6032.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6032.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6032.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6032.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6032.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6032.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6032.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6032.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6032.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6032.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6032.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6032.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6032.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6032.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6032.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6032.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6032.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6032.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6032.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6032.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6032.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6032.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6032.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6032.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6032.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6032.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6032.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6032.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6032.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6032.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6032.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6032.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6032.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6032.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6032.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6032.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6032.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6032.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6032.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6032.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6033.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6033.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6033.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6033.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6034.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6034.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6034.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6034.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6034.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6034.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6034.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6034.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6034.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6034.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6034.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6034.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6034.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6034.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6034.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6034.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6034.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6034.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6034.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6034.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6034.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6034.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6035.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6035.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6035.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6035.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6035.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6035.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6035.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6035.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6035.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6035.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6035.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6035.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6035.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6035.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6035.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6035.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6035.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6035.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6035.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6035.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6035.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6035.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6035.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6035.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6035.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6036.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6036.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6036.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6036.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6036.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6036.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6036.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6036.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6036.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6036.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6036.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6036.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6036.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6036.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6036.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6036.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6036.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6036.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6036.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6036.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6036.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6036.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6036.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6037.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6037.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6037.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6037.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6038.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6038.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6038.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6038.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6038.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6038.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6038.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6038.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6038.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6038.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6038.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6038.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6038.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6038.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6038.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6038.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6038.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6038.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6038.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6038.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6038.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6038.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6038.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6038.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6038.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6038.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6038.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6038.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6038.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6038.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6038.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6038.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6039.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6039.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6039.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6039.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6039.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6039.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6039.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6039.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6039.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6039.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6039.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6039.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6039.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6039.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6039.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6039.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6039.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6039.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6039.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6039.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6039.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6039.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6039.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6040.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6040.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6040.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6040.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6040.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6040.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6040.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6040.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6040.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6040.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6040.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6040.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6040.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6040.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6040.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6040.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6040.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6040.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6040.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6040.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6040.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6040.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6040.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6040.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6040.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6041.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6041.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6041.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6041.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6041.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6041.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6041.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6041.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6041.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6041.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6041.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6041.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6041.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6041.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6041.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6041.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6041.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6041.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6041.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6041.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6041.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6041.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6041.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6041.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6042.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6042.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6042.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6042.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6042.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6042.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6042.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6042.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6042.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6042.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6042.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6042.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6042.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6042.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6042.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6042.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6042.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6042.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6042.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6042.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6042.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6043.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6043.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6043.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6043.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6043.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6043.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6043.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6043.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6043.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6043.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6043.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6043.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6043.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6043.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6043.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6043.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6043.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6043.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6043.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6043.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6043.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6043.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6043.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6043.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6043.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6043.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6043.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6043.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6043.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6043.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6043.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6043.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6043.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6043.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6043.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6043.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6043.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6043.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6043.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6043.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6043.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6044.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6044.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6044.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6044.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6044.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6044.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55a30] >[ 6044.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55a30] width 1920 pitch 7680 (/4 1920) >[ 6044.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6044.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6044.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6044.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6044.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6044.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6044.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6044.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6044.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6044.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6044.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6044.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6044.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6044.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6044.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6045.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6045.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6045.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6045.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6045.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6045.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6045.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6045.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6045.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6045.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cb2e10] >[ 6045.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cb2e10] width 1920 pitch 7680 (/4 1920) >[ 6045.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6045.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6045.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6045.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6045.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6045.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6045.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6045.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6045.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6045.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6045.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6045.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6045.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6045.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6045.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6045.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6045.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458b720] >[ 6045.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458b720] width 1920 pitch 7680 (/4 1920) >[ 6045.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587bd0] >[ 6045.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587bd0] width 1920 pitch 7680 (/4 1920) >[ 6045.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c22940] >[ 6045.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c22940] width 1920 pitch 7680 (/4 1920) >[ 6045.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c30] >[ 6045.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c30] width 1920 pitch 7680 (/4 1920) >[ 6045.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4084de0] >[ 6045.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4084de0] width 1920 pitch 7680 (/4 1920) >[ 6046.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41eadb0] >[ 6046.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41eadb0] width 1920 pitch 7680 (/4 1920) >[ 6046.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4092d50] >[ 6046.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4092d50] width 1920 pitch 7680 (/4 1920) >[ 6046.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40894c0] >[ 6046.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40894c0] width 1920 pitch 7680 (/4 1920) >[ 6046.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x419f870] >[ 6046.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x419f870] width 1920 pitch 7680 (/4 1920) >[ 6046.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a76540] >[ 6046.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a76540] width 1920 pitch 7680 (/4 1920) >[ 6046.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92d20] >[ 6046.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92d20] width 1920 pitch 7680 (/4 1920) >[ 6046.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4745d90] >[ 6046.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4745d90] width 1920 pitch 7680 (/4 1920) >[ 6046.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35331f0] >[ 6046.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35331f0] width 1920 pitch 7680 (/4 1920) >[ 6046.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41dd150] >[ 6046.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41dd150] width 1920 pitch 7680 (/4 1920) >[ 6046.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41eb920] >[ 6046.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41eb920] width 1920 pitch 7680 (/4 1920) >[ 6046.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c55e60] >[ 6046.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c55e60] width 1920 pitch 7680 (/4 1920) >[ 6046.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44df4b0] >[ 6046.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44df4b0] width 1920 pitch 7680 (/4 1920) >[ 6046.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b8bfd0] >[ 6046.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b8bfd0] width 1920 pitch 7680 (/4 1920) >[ 6046.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4631cb0] >[ 6046.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4631cb0] width 1920 pitch 7680 (/4 1920) >[ 6046.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7d980] >[ 6046.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7d980] width 1920 pitch 7680 (/4 1920) >[ 6046.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x428cb90] >[ 6046.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x428cb90] width 1920 pitch 7680 (/4 1920) >[ 6046.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3532800] >[ 6046.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3532800] width 1920 pitch 7680 (/4 1920) >[ 6046.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43e6f90] >[ 6046.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43e6f90] width 1920 pitch 7680 (/4 1920) >[ 6046.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ef2d0] >[ 6046.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ef2d0] width 1920 pitch 7680 (/4 1920) >[ 6047.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c273d0] >[ 6047.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c273d0] width 1920 pitch 7680 (/4 1920) >[ 6047.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47d6590] >[ 6047.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47d6590] width 1920 pitch 7680 (/4 1920) >[ 6047.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f7dc0] >[ 6047.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f7dc0] width 1920 pitch 7680 (/4 1920) >[ 6047.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331c40] >[ 6047.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331c40] width 1920 pitch 7680 (/4 1920) >[ 6047.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47bc880] >[ 6047.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47bc880] width 1920 pitch 7680 (/4 1920) >[ 6047.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b8bfd0] >[ 6047.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b8bfd0] width 1920 pitch 7680 (/4 1920) >[ 6047.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f110] >[ 6047.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f110] width 1920 pitch 7680 (/4 1920) >[ 6047.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4398810] >[ 6047.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4398810] width 1920 pitch 7680 (/4 1920) >[ 6047.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d0c10] >[ 6047.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d0c10] width 1920 pitch 7680 (/4 1920) >[ 6047.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c472f0] >[ 6047.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c472f0] width 1920 pitch 7680 (/4 1920) >[ 6047.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40307d0] >[ 6047.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40307d0] width 1920 pitch 7680 (/4 1920) >[ 6047.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40894c0] >[ 6047.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40894c0] width 1920 pitch 7680 (/4 1920) >[ 6047.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426a850] >[ 6047.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426a850] width 1920 pitch 7680 (/4 1920) >[ 6047.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4135880] >[ 6047.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4135880] width 1920 pitch 7680 (/4 1920) >[ 6047.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426bc60] >[ 6047.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426bc60] width 1920 pitch 7680 (/4 1920) >[ 6047.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35331f0] >[ 6047.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35331f0] width 1920 pitch 7680 (/4 1920) >[ 6047.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426a850] >[ 6047.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426a850] width 1920 pitch 7680 (/4 1920) >[ 6047.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47bc880] >[ 6047.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47bc880] width 1920 pitch 7680 (/4 1920) >[ 6047.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c14a20] >[ 6047.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c14a20] width 1920 pitch 7680 (/4 1920) >[ 6047.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x409c1b0] >[ 6047.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x409c1b0] width 1920 pitch 7680 (/4 1920) >[ 6048.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43e6f90] >[ 6048.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43e6f90] width 1920 pitch 7680 (/4 1920) >[ 6048.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4204fd0] >[ 6048.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4204fd0] width 1920 pitch 7680 (/4 1920) >[ 6048.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43e6f90] >[ 6048.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43e6f90] width 1920 pitch 7680 (/4 1920) >[ 6048.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43238f0] >[ 6048.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43238f0] width 1920 pitch 7680 (/4 1920) >[ 6048.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4734080] >[ 6048.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4734080] width 1920 pitch 7680 (/4 1920) >[ 6048.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x474cfc0] >[ 6048.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x474cfc0] width 1920 pitch 7680 (/4 1920) >[ 6048.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe8f00] >[ 6048.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe8f00] width 1920 pitch 7680 (/4 1920) >[ 6048.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x435dc70] >[ 6048.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x435dc70] width 1920 pitch 7680 (/4 1920) >[ 6048.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426a850] >[ 6048.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426a850] width 1920 pitch 7680 (/4 1920) >[ 6048.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43e6f90] >[ 6048.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43e6f90] width 1920 pitch 7680 (/4 1920) >[ 6048.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a22a0] >[ 6048.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a22a0] width 1920 pitch 7680 (/4 1920) >[ 6048.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90420] >[ 6048.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90420] width 1920 pitch 7680 (/4 1920) >[ 6048.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3559590] >[ 6048.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3559590] width 1920 pitch 7680 (/4 1920) >[ 6048.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42725d0] >[ 6048.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42725d0] width 1920 pitch 7680 (/4 1920) >[ 6048.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ff94a0] >[ 6048.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ff94a0] width 1920 pitch 7680 (/4 1920) >[ 6048.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4631cb0] >[ 6048.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4631cb0] width 1920 pitch 7680 (/4 1920) >[ 6048.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340eb0] >[ 6048.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340eb0] width 1920 pitch 7680 (/4 1920) >[ 6048.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x435df20] >[ 6048.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x435df20] width 1920 pitch 7680 (/4 1920) >[ 6048.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cee7b0] >[ 6048.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cee7b0] width 1920 pitch 7680 (/4 1920) >[ 6048.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43992e0] >[ 6048.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43992e0] width 1920 pitch 7680 (/4 1920) >[ 6049.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48026e0] >[ 6049.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48026e0] width 1920 pitch 7680 (/4 1920) >[ 6049.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43e6f90] >[ 6049.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43e6f90] width 1920 pitch 7680 (/4 1920) >[ 6049.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4204fd0] >[ 6049.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4204fd0] width 1920 pitch 7680 (/4 1920) >[ 6049.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6c290] >[ 6049.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6c290] width 1920 pitch 7680 (/4 1920) >[ 6049.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c745e0] >[ 6049.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c745e0] width 1920 pitch 7680 (/4 1920) >[ 6049.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401f2b0] >[ 6049.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401f2b0] width 1920 pitch 7680 (/4 1920) >[ 6049.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f9f0] >[ 6049.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f9f0] width 1920 pitch 7680 (/4 1920) >[ 6049.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ef2d0] >[ 6049.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ef2d0] width 1920 pitch 7680 (/4 1920) >[ 6049.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2b8bfd0] >[ 6049.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2b8bfd0] width 1920 pitch 7680 (/4 1920) >[ 6049.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cd2070] >[ 6049.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cd2070] width 1920 pitch 7680 (/4 1920) >[ 6049.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90420] >[ 6049.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90420] width 1920 pitch 7680 (/4 1920) >[ 6049.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cd0970] >[ 6049.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cd0970] width 1920 pitch 7680 (/4 1920) >[ 6049.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d3d0] >[ 6049.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d3d0] width 1920 pitch 7680 (/4 1920) >[ 6049.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4260530] >[ 6049.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4260530] width 1920 pitch 7680 (/4 1920) >[ 6049.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x406f9f0] >[ 6049.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x406f9f0] width 1920 pitch 7680 (/4 1920) >[ 6049.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49cd490] >[ 6049.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49cd490] width 1920 pitch 7680 (/4 1920) >[ 6049.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4084de0] >[ 6049.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4084de0] width 1920 pitch 7680 (/4 1920) >[ 6049.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331a10] >[ 6049.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331a10] width 1920 pitch 7680 (/4 1920) >[ 6049.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40307d0] >[ 6049.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40307d0] width 1920 pitch 7680 (/4 1920) >[ 6049.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4331a10] >[ 6049.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4331a10] width 1920 pitch 7680 (/4 1920) >[ 6050.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x427c880] >[ 6050.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x427c880] width 1920 pitch 7680 (/4 1920) >[ 6050.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a20e0] >[ 6050.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a20e0] width 1920 pitch 7680 (/4 1920) >[ 6050.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c6090] >[ 6050.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c6090] width 1920 pitch 7680 (/4 1920) >[ 6050.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c53050] >[ 6050.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c53050] width 1920 pitch 7680 (/4 1920) >[ 6050.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426acf0] >[ 6050.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426acf0] width 1920 pitch 7680 (/4 1920) >[ 6050.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x425bf60] >[ 6050.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x425bf60] width 1920 pitch 7680 (/4 1920) >[ 6050.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4146b90] >[ 6050.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4146b90] width 1920 pitch 7680 (/4 1920) >[ 6050.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x407f110] >[ 6050.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x407f110] width 1920 pitch 7680 (/4 1920) >[ 6050.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c11a00] >[ 6050.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c11a00] width 1920 pitch 7680 (/4 1920) >[ 6050.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a76540] >[ 6050.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a76540] width 1920 pitch 7680 (/4 1920) >[ 6050.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6400] >[ 6050.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6400] width 1920 pitch 7680 (/4 1920) >[ 6050.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4353e40] >[ 6050.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4353e40] width 1920 pitch 7680 (/4 1920) >[ 6050.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x44cd8b0] >[ 6050.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x44cd8b0] width 1920 pitch 7680 (/4 1920) >[ 6050.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42c3bf0] >[ 6050.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42c3bf0] width 1920 pitch 7680 (/4 1920) >[ 6050.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4023ae0] >[ 6050.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4023ae0] width 1920 pitch 7680 (/4 1920) >[ 6050.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4052890] >[ 6050.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4052890] width 1920 pitch 7680 (/4 1920) >[ 6050.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a6bf60] >[ 6050.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a6bf60] width 1920 pitch 7680 (/4 1920) >[ 6050.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddf10] >[ 6050.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddf10] width 1920 pitch 7680 (/4 1920) >[ 6050.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40de240] >[ 6050.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40de240] width 1920 pitch 7680 (/4 1920) >[ 6050.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x435df20] >[ 6050.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x435df20] width 1920 pitch 7680 (/4 1920) >[ 6051.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a8860] >[ 6051.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a8860] width 1920 pitch 7680 (/4 1920) >[ 6051.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbcd20] >[ 6051.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbcd20] width 1920 pitch 7680 (/4 1920) >[ 6051.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cd2800] >[ 6051.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cd2800] width 1920 pitch 7680 (/4 1920) >[ 6051.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033020] >[ 6051.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033020] width 1920 pitch 7680 (/4 1920) >[ 6051.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef8fe0] >[ 6051.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef8fe0] width 1920 pitch 7680 (/4 1920) >[ 6051.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40894c0] >[ 6051.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40894c0] width 1920 pitch 7680 (/4 1920) >[ 6051.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426a850] >[ 6051.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426a850] width 1920 pitch 7680 (/4 1920) >[ 6051.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92d20] >[ 6051.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92d20] width 1920 pitch 7680 (/4 1920) >[ 6051.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82f20] >[ 6051.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82f20] width 1920 pitch 7680 (/4 1920) >[ 6051.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43ef2d0] >[ 6051.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43ef2d0] width 1920 pitch 7680 (/4 1920) >[ 6051.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061220] >[ 6051.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061220] width 1920 pitch 7680 (/4 1920) >[ 6051.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ef880] >[ 6051.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ef880] width 1920 pitch 7680 (/4 1920) >[ 6051.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4364730] >[ 6051.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4364730] width 1920 pitch 7680 (/4 1920) >[ 6051.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x473dcc0] >[ 6051.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x473dcc0] width 1920 pitch 7680 (/4 1920) >[ 6051.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c42bb0] >[ 6051.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c42bb0] width 1920 pitch 7680 (/4 1920) >[ 6051.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6051.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6051.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6051.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6051.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6051.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6051.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6051.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6051.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6051.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6051.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6051.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6052.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6052.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6052.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6052.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6053.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6053.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6053.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6053.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6053.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6053.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6053.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6053.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6053.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6053.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6053.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4530] >[ 6053.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4530] width 1920 pitch 7680 (/4 1920) >[ 6053.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b44d0] >[ 6053.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b44d0] width 1920 pitch 7680 (/4 1920) >[ 6053.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c46430] >[ 6053.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c46430] width 1920 pitch 7680 (/4 1920) >[ 6053.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e0d0] >[ 6053.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e0d0] width 1920 pitch 7680 (/4 1920) >[ 6053.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6053.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6053.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbfc00] >[ 6053.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbfc00] width 1920 pitch 7680 (/4 1920) >[ 6053.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6053.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6053.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6053.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6053.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6053.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6053.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6053.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6053.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6053.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6053.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbfc00] >[ 6053.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbfc00] width 1920 pitch 7680 (/4 1920) >[ 6053.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6053.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6053.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbfc00] >[ 6053.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbfc00] width 1920 pitch 7680 (/4 1920) >[ 6053.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6053.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6053.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e0d0] >[ 6053.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e0d0] width 1920 pitch 7680 (/4 1920) >[ 6054.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6054.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6054.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6054.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6054.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6054.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6054.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6054.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6054.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbfc00] >[ 6054.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbfc00] width 1920 pitch 7680 (/4 1920) >[ 6054.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6054.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6054.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbfc00] >[ 6054.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbfc00] width 1920 pitch 7680 (/4 1920) >[ 6054.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6054.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6054.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6054.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6054.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc1540] >[ 6054.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc1540] width 1920 pitch 7680 (/4 1920) >[ 6054.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6054.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6054.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc1540] >[ 6054.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc1540] width 1920 pitch 7680 (/4 1920) >[ 6054.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbfc00] >[ 6054.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbfc00] width 1920 pitch 7680 (/4 1920) >[ 6054.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6054.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6054.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6054.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6054.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6054.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6054.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6054.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6054.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6054.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6054.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc1540] >[ 6054.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc1540] width 1920 pitch 7680 (/4 1920) >[ 6054.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cbfc00] >[ 6054.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cbfc00] width 1920 pitch 7680 (/4 1920) >[ 6054.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c8c0] >[ 6054.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c8c0] width 1920 pitch 7680 (/4 1920) >[ 6055.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6055.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6055.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476ff30] >[ 6055.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476ff30] width 1920 pitch 7680 (/4 1920) >[ 6055.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6055.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6055.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476ff30] >[ 6055.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476ff30] width 1920 pitch 7680 (/4 1920) >[ 6055.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6055.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6055.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6055.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6055.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6055.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6055.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6055.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6055.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6055.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6055.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6055.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6055.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6055.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6055.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6055.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6055.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6055.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6055.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6055.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6055.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6055.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6055.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6055.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6055.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6055.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6055.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6055.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6055.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6055.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6055.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6055.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6055.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6055.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6055.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6055.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6056.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6056.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6056.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6056.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6056.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6056.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6056.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6056.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6056.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6056.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6056.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6056.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6056.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6056.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cff40] >[ 6056.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cff40] width 1920 pitch 7680 (/4 1920) >[ 6056.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cff40] >[ 6056.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cff40] width 1920 pitch 7680 (/4 1920) >[ 6056.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6056.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6056.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6056.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cfb00] >[ 6056.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cfb00] width 1920 pitch 7680 (/4 1920) >[ 6056.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6056.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6057.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6057.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6057.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6057.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6057.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6057.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6057.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6057.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6057.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6057.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6057.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6057.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6057.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6057.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6057.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6057.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6057.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6057.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6057.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6057.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6057.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6057.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6057.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6057.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6057.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6057.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6057.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6057.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6057.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6057.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6057.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6057.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6057.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6057.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6057.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6057.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6057.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6057.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6057.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6057.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6057.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6057.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6057.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6057.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6058.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6058.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6058.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6058.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6058.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6058.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6058.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6058.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6058.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6058.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6058.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6058.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6058.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6058.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6058.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6058.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6058.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6058.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6058.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6058.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6058.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6058.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6058.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6058.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6058.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c120] >[ 6058.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c120] width 1920 pitch 7680 (/4 1920) >[ 6058.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6058.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6059.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6059.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6059.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6059.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6059.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6059.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6059.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6059.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6059.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6059.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6059.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6059.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6059.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6059.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6059.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6059.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6059.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c8a0] >[ 6059.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c8a0] width 1920 pitch 7680 (/4 1920) >[ 6059.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6059.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6060.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6060.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6060.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6060.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6060.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6060.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6060.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6060.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6060.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6060.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6060.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6060.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6060.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6060.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6060.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6060.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6060.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6060.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6060.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6060.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6060.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6060.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6060.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6060.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6060.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6060.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6060.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6060.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6060.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6060.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6060.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6060.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6060.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6060.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6060.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6060.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6060.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6060.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6060.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6060.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6060.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6060.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6060.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6060.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6060.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6061.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6061.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6061.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6061.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6061.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6061.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6061.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6061.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6061.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6061.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6061.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6061.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6061.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6061.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6061.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6061.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c8c0] >[ 6061.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c8c0] width 1920 pitch 7680 (/4 1920) >[ 6061.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c8c0] >[ 6061.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c8c0] width 1920 pitch 7680 (/4 1920) >[ 6061.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6061.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6061.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6061.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6061.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6061.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6061.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6061.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6061.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6062.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6062.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6062.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6062.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6062.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6062.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6062.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6062.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6062.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6062.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c8c0] >[ 6062.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c8c0] width 1920 pitch 7680 (/4 1920) >[ 6063.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6063.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6063.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c8c0] >[ 6063.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c8c0] width 1920 pitch 7680 (/4 1920) >[ 6063.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6063.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6063.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6063.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6063.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6063.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6063.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6063.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6063.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6063.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6063.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6063.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6063.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6063.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6063.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6063.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6063.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6063.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6063.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6063.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6063.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6063.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6063.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6063.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6063.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6063.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6063.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6063.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6063.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6063.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6063.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6063.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6063.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6063.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6063.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6063.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6063.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6063.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6063.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6063.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6064.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6064.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6064.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6064.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6064.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6064.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6064.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6064.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6064.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6064.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c29910] >[ 6064.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c29910] width 1920 pitch 7680 (/4 1920) >[ 6064.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6064.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6064.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6064.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6064.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6064.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6064.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6064.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6064.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6064.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6064.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c29910] >[ 6064.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c29910] width 1920 pitch 7680 (/4 1920) >[ 6064.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6064.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6064.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6065.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6065.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6065.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6065.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6065.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6065.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6065.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6065.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6065.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6065.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6065.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6065.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6065.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6065.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6065.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6065.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6065.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6065.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6065.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6065.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6065.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6065.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6065.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6065.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6065.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6065.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6065.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6066.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6066.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6066.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6066.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6066.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6066.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6066.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6066.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6066.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6066.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6066.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6066.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6066.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457bbb0] >[ 6066.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457bbb0] width 1920 pitch 7680 (/4 1920) >[ 6066.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457bbb0] >[ 6066.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457bbb0] width 1920 pitch 7680 (/4 1920) >[ 6066.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6066.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6066.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6066.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6066.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6066.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6066.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6067.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6067.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6067.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6067.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6067.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6067.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6067.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6067.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6067.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6067.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6067.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6067.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6067.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6067.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6067.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6067.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6067.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6067.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6067.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6067.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6067.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6067.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6068.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6068.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6068.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6068.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6068.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6068.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6068.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6068.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6068.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6068.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6068.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6068.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6068.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6068.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6068.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6068.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6068.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6068.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6068.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6068.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6068.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6068.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6068.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6068.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6068.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6068.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6068.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6068.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6068.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6068.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6068.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6068.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6068.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6068.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6068.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6068.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6068.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6068.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6068.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6068.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6068.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6068.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6068.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6068.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6069.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6069.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6069.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6069.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6069.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6069.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6069.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6069.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6069.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6069.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6069.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6069.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6069.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6069.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6069.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6069.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6069.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6069.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6069.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6069.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6069.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6069.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6069.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6069.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6069.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6069.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6069.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c29910] >[ 6069.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c29910] width 1920 pitch 7680 (/4 1920) >[ 6069.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6069.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6069.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6069.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6069.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6069.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6069.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6069.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6069.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6069.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6069.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6069.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6069.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6069.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6069.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6069.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6069.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6070.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6070.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6070.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6070.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6070.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6070.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6070.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6070.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6070.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6070.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6070.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6070.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6070.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6070.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6070.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6070.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6070.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6070.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6070.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6070.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6070.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6070.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6070.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6070.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6070.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6070.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6070.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6070.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6070.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6070.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6070.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6070.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6070.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6070.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6070.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6070.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6070.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6070.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6070.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6070.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6070.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6070.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6070.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6070.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6070.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6071.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6071.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6071.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6071.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6071.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6071.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6071.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6071.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6071.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4086280] >[ 6071.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4086280] width 1920 pitch 7680 (/4 1920) >[ 6071.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6071.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6071.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6071.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6071.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6071.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6071.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6071.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6071.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc14a0] >[ 6071.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc14a0] width 1920 pitch 7680 (/4 1920) >[ 6071.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6071.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6071.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6071.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6071.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4277620] >[ 6071.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4277620] width 1920 pitch 7680 (/4 1920) >[ 6071.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6071.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6071.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426ad30] >[ 6071.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426ad30] width 1920 pitch 7680 (/4 1920) >[ 6071.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6071.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6071.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6071.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6071.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6071.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6071.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6071.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6071.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6071.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6071.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6071.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6071.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6071.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6071.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6071.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6072.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6072.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6072.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6072.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6072.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6072.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6072.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6072.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6072.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321a0] >[ 6072.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321a0] width 1920 pitch 7680 (/4 1920) >[ 6072.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34efe20] >[ 6072.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34efe20] width 1920 pitch 7680 (/4 1920) >[ 6672.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6672.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6672.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6672.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6672.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6672.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6672.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6672.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6672.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f43f0] >[ 6672.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f43f0] width 1920 pitch 7680 (/4 1920) >[ 6672.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6672.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6672.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6672.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6672.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6672.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6672.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6672.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6672.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49c7fc0] >[ 6672.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49c7fc0] width 1920 pitch 7680 (/4 1920) >[ 6672.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6672.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6672.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49c7fc0] >[ 6672.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49c7fc0] width 1920 pitch 7680 (/4 1920) >[ 6672.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6672.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6672.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581a50] >[ 6672.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581a50] width 1920 pitch 7680 (/4 1920) >[ 6673.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6673.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6673.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581a50] >[ 6673.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581a50] width 1920 pitch 7680 (/4 1920) >[ 6673.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6673.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6673.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581a50] >[ 6673.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581a50] width 1920 pitch 7680 (/4 1920) >[ 6673.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6673.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6673.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581a50] >[ 6673.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581a50] width 1920 pitch 7680 (/4 1920) >[ 6673.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6673.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6673.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6673.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6673.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6673.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6673.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6673.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6673.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6673.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6673.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6673.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6673.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6673.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6673.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6673.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6673.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6673.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6673.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6673.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6673.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6673.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6673.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6673.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6673.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6673.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6673.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6673.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6674.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6674.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6674.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6674.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6674.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6674.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6674.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6674.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6674.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6674.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6674.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6674.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6674.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49c7dc0] >[ 6674.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49c7dc0] width 1920 pitch 7680 (/4 1920) >[ 6674.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6674.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6674.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49c7dc0] >[ 6674.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49c7dc0] width 1920 pitch 7680 (/4 1920) >[ 6674.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6674.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6674.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6674.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6674.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6674.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6674.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6674.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6674.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6674.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6674.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6674.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6674.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49c7dc0] >[ 6674.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49c7dc0] width 1920 pitch 7680 (/4 1920) >[ 6674.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f32f0] >[ 6674.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f32f0] width 1920 pitch 7680 (/4 1920) >[ 6674.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6674.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6674.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2750] >[ 6674.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2750] width 1920 pitch 7680 (/4 1920) >[ 6674.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6674.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6674.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2750] >[ 6674.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2750] width 1920 pitch 7680 (/4 1920) >[ 6674.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6674.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6674.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49c7dc0] >[ 6674.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49c7dc0] width 1920 pitch 7680 (/4 1920) >[ 6674.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6674.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6675.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49c7dc0] >[ 6675.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49c7dc0] width 1920 pitch 7680 (/4 1920) >[ 6675.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6675.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6675.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6675.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6675.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6675.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6675.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582470] >[ 6675.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582470] width 1920 pitch 7680 (/4 1920) >[ 6675.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6675.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6675.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f43f0] >[ 6675.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f43f0] width 1920 pitch 7680 (/4 1920) >[ 6675.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6675.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6675.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6675.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6675.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6675.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6675.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6675.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6675.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6675.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6675.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6675.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6675.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6675.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6675.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6675.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6675.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6675.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6675.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6675.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6675.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6675.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6675.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6675.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6675.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6675.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6675.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6675.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6675.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6675.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6675.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fdf30] >[ 6675.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fdf30] width 1920 pitch 7680 (/4 1920) >[ 6675.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6675.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6675.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fdf30] >[ 6675.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fdf30] width 1920 pitch 7680 (/4 1920) >[ 6676.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6676.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6676.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6676.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6676.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6676.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6676.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6676.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6676.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6676.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6676.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6676.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6676.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6676.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6676.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6676.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6676.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6676.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6676.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6676.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6676.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6676.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6676.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6676.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6676.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6676.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6676.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6676.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6676.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6676.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6676.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6676.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6676.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6676.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6676.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6676.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6676.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6676.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6676.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6676.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6676.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6676.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6676.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6676.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6676.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6676.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6676.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6676.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6677.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49ff010] >[ 6677.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49ff010] width 1920 pitch 7680 (/4 1920) >[ 6677.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6677.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6677.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49ff010] >[ 6677.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49ff010] width 1920 pitch 7680 (/4 1920) >[ 6677.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6677.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6677.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6677.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6677.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6677.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6677.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6677.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6677.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6677.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6677.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6677.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6677.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6677.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6677.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6677.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6677.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6677.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6677.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6677.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6677.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6677.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6677.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6677.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6677.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6677.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6677.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6677.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6677.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6677.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6677.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6677.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6677.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6677.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6677.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6677.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6677.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6677.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6677.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6677.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6677.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6677.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6678.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6678.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6678.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6678.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6678.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6678.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6678.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6678.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6678.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6678.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6678.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6678.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6678.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6678.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6678.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6678.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6678.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6678.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6678.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6678.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6678.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6678.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6678.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6678.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6678.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6678.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6678.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6678.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6678.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6678.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6678.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6678.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6678.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6678.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6678.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6678.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6678.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6678.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6678.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6678.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6678.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6678.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6678.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6678.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6678.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6678.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6678.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6678.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6679.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6679.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6679.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6679.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6679.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6679.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6679.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6679.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6679.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6679.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6679.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6679.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6679.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6679.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6679.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6679.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6679.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6679.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6679.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6679.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6679.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6679.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6679.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6679.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6679.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6679.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6679.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6679.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6679.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6679.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6679.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6680.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6680.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6680.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6680.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6680.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6680.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6680.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6680.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6680.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6680.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6680.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6680.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6680.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6680.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6680.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6680.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6680.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6680.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6680.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6680.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6680.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6680.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6680.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6680.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6680.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6680.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6680.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6680.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6680.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6680.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6680.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6680.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6680.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6680.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6680.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6680.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6680.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6680.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6680.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6680.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6680.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6680.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6680.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6680.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6680.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6680.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6680.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6680.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6681.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6681.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6681.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6681.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6681.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6681.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6681.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6681.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6681.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6681.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6681.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6681.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6681.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6681.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6681.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6681.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6681.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6681.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6681.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6681.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6681.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6681.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6681.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6681.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6681.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6681.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6681.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6681.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6681.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6681.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6681.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6681.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6681.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6681.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6681.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6681.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6681.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6681.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6681.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6681.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6682.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6682.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6682.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6682.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6682.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6682.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6682.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6682.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6682.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6682.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6682.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6682.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6683.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6683.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6683.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6683.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6683.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6683.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6683.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6683.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6683.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6683.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6683.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6683.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6683.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6683.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6683.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6683.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6683.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6683.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6683.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6683.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6683.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6683.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6683.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6683.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6683.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6683.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6683.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6683.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6683.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6683.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6683.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6683.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6683.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6683.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6683.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6683.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6683.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6683.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6683.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6683.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6683.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6683.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6683.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6683.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6683.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6683.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6683.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6683.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6683.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6684.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6684.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6684.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6684.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6684.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6684.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6684.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6684.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6684.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6684.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6684.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6684.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6684.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6684.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6684.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6684.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6684.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6684.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6684.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6684.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6684.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6684.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6684.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6684.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6684.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6684.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6684.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6684.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6684.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6684.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6685.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6685.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6685.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6685.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6685.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6685.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6685.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6685.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6685.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6685.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6685.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6685.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6685.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6685.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6685.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6685.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6685.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6685.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6685.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6685.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6685.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6685.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6685.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6685.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6685.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6685.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6685.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6685.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6685.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6685.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6685.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6685.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6685.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6685.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6685.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6685.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6685.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6685.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6685.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6685.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6685.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6685.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6685.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6685.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6685.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6685.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6685.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6685.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6686.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6686.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6686.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6686.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6687.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6687.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6687.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6687.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6687.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6687.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6687.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6687.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6687.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48bcfa0] >[ 6687.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48bcfa0] width 1920 pitch 7680 (/4 1920) >[ 6687.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6687.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6687.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48bcfa0] >[ 6687.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48bcfa0] width 1920 pitch 7680 (/4 1920) >[ 6687.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6687.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6687.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6687.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6687.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6687.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6687.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6687.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6687.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6687.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6687.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6687.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6687.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6687.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6687.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6687.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6687.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6687.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6688.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6688.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6688.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6688.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6688.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6688.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6688.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6688.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6688.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6688.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6688.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6688.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6688.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6688.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6688.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6688.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6688.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6688.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6688.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6688.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6688.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6688.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6688.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6688.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6688.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6688.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6688.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6688.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6688.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6688.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6688.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6688.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6688.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6688.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6688.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6688.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6688.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6688.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6688.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6688.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6688.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6688.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6688.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6688.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6688.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6688.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6688.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6688.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6689.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6689.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6689.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6689.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6689.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6689.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6689.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6689.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6689.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6689.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6689.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6689.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6689.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6689.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6689.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6689.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6689.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6689.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6689.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6689.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6689.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6689.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6689.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6689.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6689.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6689.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6689.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6689.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6689.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6689.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6689.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6689.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6689.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6689.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6689.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6689.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6689.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6689.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6689.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6689.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6689.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6689.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6689.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6689.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6689.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6689.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6689.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6689.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6690.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6690.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6690.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6690.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6690.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6690.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6690.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6690.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6690.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6690.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6690.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6690.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6690.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6690.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6690.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6690.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6690.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6690.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6690.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6690.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6690.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6690.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6690.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6690.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6690.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6690.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6690.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6690.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6690.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6690.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6690.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6690.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6690.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6690.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6690.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6690.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6690.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6690.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6690.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6690.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6690.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6690.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6690.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6690.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6690.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6690.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6690.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6690.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6691.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6691.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6691.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6691.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6691.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6691.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6691.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6691.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6691.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6691.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6691.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6691.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6691.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6691.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6691.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6691.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6691.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6691.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6691.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6691.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6691.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6691.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6691.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6691.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6691.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6691.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6691.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6691.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6691.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6691.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6691.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6691.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6691.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6691.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6691.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6691.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6691.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6691.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6691.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6691.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6691.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6691.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6691.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6691.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6691.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6691.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6691.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6691.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6692.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6692.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6692.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6692.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6692.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6692.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6692.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6692.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6692.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6692.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6692.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6692.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6692.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6692.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6692.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6692.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6692.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6692.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6692.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6692.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6692.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6692.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6692.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6692.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6692.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6692.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6692.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6692.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6692.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6692.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6692.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6692.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6692.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6692.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6692.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6692.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6692.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6692.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6692.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6692.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6692.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6692.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6692.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6692.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6692.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6692.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6693.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6693.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6693.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6693.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6693.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6693.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6693.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6693.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6693.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6693.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6693.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6694.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6694.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6694.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6694.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6694.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6694.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6694.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6694.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6694.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6694.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6694.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6694.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6694.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6694.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6694.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6694.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6694.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6694.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6694.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6694.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6694.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6694.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6694.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6694.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6694.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6694.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6694.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6694.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6694.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6694.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6694.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6694.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6694.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6694.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6694.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6694.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6694.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6694.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6694.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6694.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6694.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6694.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6694.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6694.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6694.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6694.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6694.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6694.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6695.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6695.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6695.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6695.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6695.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6695.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6695.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6695.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6695.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6695.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6696.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6696.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6696.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6696.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6696.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6696.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6696.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6696.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6696.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6696.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6696.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6696.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6696.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6696.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6696.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6696.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6696.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6696.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6696.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6696.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6696.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6696.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6696.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6696.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6696.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6696.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6696.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6696.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6696.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6696.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6696.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6696.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6696.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6696.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6696.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6696.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6696.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6696.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6696.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6696.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6696.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6696.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6696.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6696.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6696.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6696.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6696.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6696.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6697.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6697.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6697.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6697.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6697.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6697.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6697.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6697.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6697.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6697.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6697.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6697.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6697.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6697.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6697.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6697.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6697.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6697.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6697.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6697.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6697.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6697.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6697.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6697.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6697.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6697.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6697.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6697.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6697.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6697.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6697.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6697.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6697.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6697.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6697.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6697.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6697.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6697.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6697.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6697.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6697.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6697.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6697.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6697.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6697.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6697.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6697.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6697.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6698.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6698.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6698.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6698.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6698.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6698.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6698.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6698.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6698.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6698.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6698.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6698.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6698.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6698.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6698.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6698.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6698.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6698.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6698.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6698.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6698.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6698.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6698.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6698.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6698.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6698.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6698.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6698.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6698.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6698.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6698.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6698.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6698.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6698.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6698.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6698.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6698.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6698.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6698.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6698.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6698.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6698.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6698.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6698.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6698.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6698.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6698.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6699.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6699.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6699.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6699.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6699.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6699.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6699.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6699.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6699.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6699.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6699.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6699.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6699.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6699.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6699.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6699.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6699.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6699.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6699.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6699.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6699.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6699.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6699.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6699.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6699.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6699.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6699.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6699.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6699.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6699.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6699.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6699.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6699.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6699.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6699.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6699.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6699.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6699.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6699.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6699.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6699.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6699.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6699.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6699.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6699.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6699.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6699.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6700.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6700.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6700.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6700.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6700.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6700.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6700.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6700.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6700.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6700.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6700.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6700.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6700.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6700.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6700.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6700.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6700.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6700.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6700.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6700.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6700.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6700.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6700.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6700.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6700.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6700.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6700.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6700.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6700.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6700.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6700.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6700.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6701.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6701.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6701.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6701.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6701.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6701.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6701.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6701.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6701.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6701.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6701.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6701.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6701.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6701.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6701.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6701.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6701.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6701.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6701.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6701.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6701.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6701.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6701.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6701.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6701.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6701.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6701.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6701.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6701.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6701.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6701.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6701.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6701.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6701.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6701.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6701.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6701.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6701.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6701.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6701.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6701.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6701.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6701.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6701.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6701.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6701.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6701.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6701.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6702.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6702.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6702.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6702.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6702.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6702.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6702.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6702.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6702.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6702.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6702.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6702.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6702.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6702.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6702.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6702.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6702.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6702.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6702.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6702.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6702.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6702.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6702.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6702.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6702.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6702.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6702.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6702.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6702.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6703.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6703.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6703.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6703.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6703.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6703.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6703.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6703.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6703.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6703.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6703.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6703.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6703.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6703.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6703.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6703.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6703.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6703.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6703.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6703.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6703.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6703.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6703.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6703.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6703.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6703.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6703.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6703.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6703.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6703.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6703.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6703.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6704.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6704.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6704.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6704.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6704.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6704.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6704.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6704.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6704.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6704.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6704.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6704.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6704.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6704.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6704.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6704.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6704.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6704.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6704.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6704.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6704.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6704.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6704.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6704.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6704.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6704.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6704.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6704.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6704.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6704.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6704.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6704.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6704.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6704.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6704.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6704.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6704.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6704.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6704.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6704.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6704.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6704.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6704.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6704.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6704.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6704.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6704.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6704.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6704.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6705.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6705.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6705.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6705.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6705.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6705.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6705.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6705.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6705.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6705.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6705.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6705.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6705.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6705.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6705.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6705.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6705.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6705.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6705.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6705.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6705.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6705.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6705.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6705.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6705.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6705.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6705.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6705.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6705.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6705.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6705.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6705.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6705.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6705.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6705.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6705.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6705.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6705.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6705.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6705.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6705.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6705.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6705.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6705.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6705.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6705.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6705.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6705.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6706.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6706.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6706.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6706.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6706.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6706.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6706.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6706.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6706.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6706.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6706.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6706.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6706.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6706.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6706.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6706.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6706.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6706.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6706.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6706.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6706.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6706.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6706.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6706.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6706.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6706.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6706.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6706.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6706.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6706.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6706.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6706.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6706.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6706.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6706.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6706.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6706.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6706.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6706.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6706.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6706.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6706.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6706.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6706.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6706.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6706.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6706.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6706.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6706.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6706.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6707.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6707.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6707.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6707.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6707.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6707.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6707.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6707.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6707.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6707.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6707.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6707.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6707.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6707.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6707.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6707.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6707.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6707.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6707.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6707.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6707.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6707.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6707.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6707.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6707.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6707.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6707.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6707.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6707.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6707.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6707.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6707.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6707.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6707.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6707.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6707.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6707.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6707.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6707.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6707.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6708.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6708.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6708.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6708.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6708.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6708.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6708.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6708.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6708.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6708.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6708.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6708.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6708.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6708.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6708.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6708.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6708.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6708.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6708.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6708.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6708.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6708.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6708.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6708.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6708.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6708.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6708.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6708.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6708.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6708.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6708.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6708.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6708.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6708.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6708.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6708.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6708.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6708.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6708.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6708.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6708.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6708.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6708.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6708.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6708.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6708.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6708.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6708.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6709.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6709.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6709.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6709.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6709.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6709.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6709.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6709.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6709.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6709.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6709.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6709.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6709.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6709.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6709.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6709.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6709.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6709.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6709.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6709.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6709.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6709.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6709.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6709.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6709.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6709.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6709.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6709.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6709.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6709.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6709.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6710.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6710.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6710.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6710.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6710.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6710.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6710.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6710.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6710.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6710.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6710.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6710.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6710.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6710.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6710.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6710.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6710.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6710.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6710.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6710.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6710.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6710.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6710.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6710.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6710.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6710.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6710.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6710.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6710.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6710.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6710.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6710.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6710.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6710.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6710.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6710.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6710.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6710.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6710.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6710.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6710.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6710.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6710.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6710.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6710.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6710.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6710.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6710.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6711.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6711.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6711.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6711.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6711.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6711.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6711.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6711.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6711.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6711.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6711.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6711.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6711.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6711.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6711.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6711.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6711.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6711.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6711.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6711.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6711.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6711.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6711.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6711.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6711.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6711.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6711.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6711.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6711.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6711.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6712.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6712.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6712.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6712.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6712.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6712.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6712.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6712.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6712.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6712.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6712.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6712.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6712.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6712.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6712.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6712.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6712.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6712.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6712.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6712.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6712.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6712.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6712.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6712.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6712.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6712.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6712.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6712.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6712.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6712.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6712.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6712.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6712.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6712.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6712.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6712.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6712.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6712.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6712.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6712.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6712.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6712.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6712.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6712.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6712.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6712.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6712.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6712.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6713.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6713.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6713.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6713.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6713.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6713.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6713.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6713.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6713.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6713.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6713.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6713.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6713.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6713.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6713.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6713.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6713.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6713.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6713.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6713.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6713.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6713.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6713.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6713.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6713.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6713.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6713.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6713.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6713.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6713.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6713.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6713.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6713.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6713.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6713.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6713.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6713.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6713.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6713.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6713.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6713.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6713.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6713.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6713.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6713.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6713.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6713.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6713.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6714.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6714.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6714.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6714.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6714.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6714.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6714.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6714.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6714.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6714.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6714.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6714.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6714.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6714.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6714.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6714.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6714.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6714.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6714.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6714.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6714.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6714.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6714.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6714.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6714.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6714.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6714.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6714.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6714.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6714.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6714.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6714.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6714.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6714.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6714.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6714.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6714.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6714.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6714.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6714.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6714.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6714.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6714.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6714.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6714.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6714.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6714.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6715.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6715.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6715.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6715.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6715.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6715.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6715.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6715.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6715.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6715.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6715.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6715.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6715.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6715.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6715.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6715.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6715.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6715.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6715.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6715.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6715.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6715.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6715.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6715.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6715.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6715.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6715.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6715.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6715.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6715.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6715.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6715.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6715.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6715.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6715.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6715.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6715.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6715.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6715.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6715.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6715.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6715.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6715.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6715.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6715.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6715.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6715.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6715.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6715.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6716.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6716.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6716.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6716.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6716.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6716.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6716.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6716.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6716.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6716.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6716.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6716.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6716.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6716.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6716.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6716.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6716.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6716.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6716.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6716.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6716.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6716.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6716.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6716.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6716.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6716.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6716.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6716.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6716.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6716.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6716.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6716.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6716.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6716.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6716.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6716.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6716.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6716.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6716.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6716.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6716.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6716.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6716.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6716.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6716.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6716.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6716.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6716.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6716.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6717.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6717.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6717.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6717.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6717.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6717.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6717.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6717.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6717.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6717.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6717.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6717.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6717.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6717.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6717.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6717.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6717.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6717.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6717.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6717.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6717.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6717.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6717.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6717.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6717.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6717.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6717.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6717.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6717.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6717.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6717.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6717.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6717.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6718.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6718.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6718.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6718.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6718.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6718.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6718.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6718.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6718.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6718.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6718.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6718.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6718.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6718.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6718.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6718.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6718.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6718.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6718.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6718.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6718.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6718.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6718.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6718.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6718.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6718.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6718.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6718.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6718.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6718.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6719.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6719.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6719.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6719.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6719.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6719.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6719.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6719.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6719.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6719.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6719.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6719.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6719.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6719.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6719.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6719.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6719.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6719.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6719.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6719.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6719.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6719.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6719.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6719.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6719.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6719.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6719.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6719.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6719.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6719.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6719.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6719.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6719.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6719.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6719.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6719.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6719.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6719.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6719.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6719.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6719.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6719.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6719.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6719.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6719.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6719.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6719.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6720.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6720.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6720.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6720.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6720.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6720.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6720.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6720.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6720.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6720.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6720.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6720.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6720.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6720.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6720.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6720.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6720.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6720.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6720.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6720.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6720.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6720.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6720.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6720.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6720.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6720.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6720.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6720.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6720.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6720.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6720.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6721.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6721.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6721.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6721.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6721.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6721.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6721.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6721.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6721.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6721.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6721.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6721.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6721.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6721.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6721.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6721.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6721.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6721.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6721.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6721.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6721.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6721.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6721.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6721.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6721.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6721.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6721.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6721.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6721.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6721.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6721.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6721.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6721.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6721.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6721.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6721.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6721.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6721.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6721.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6721.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6721.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6721.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6721.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6721.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6721.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6721.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6721.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6721.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6722.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6722.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6722.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6722.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6722.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6722.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6722.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6722.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6722.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6722.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6722.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6722.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6722.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6722.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6722.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6722.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6722.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6722.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6722.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6722.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6722.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6722.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6722.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6722.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6722.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6722.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6722.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6722.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6722.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6722.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6722.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6722.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6722.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6722.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6722.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6722.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6722.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6722.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6722.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6722.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6722.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6722.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6722.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6722.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6722.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6722.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6722.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6722.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6723.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6723.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6723.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6723.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6723.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6723.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6723.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6723.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6723.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6723.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6723.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6723.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6723.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6723.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6723.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6723.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6723.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6723.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6723.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6723.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6723.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6723.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6723.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6723.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6723.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6723.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6723.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6723.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6723.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6723.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6723.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6723.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6723.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6723.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6723.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6723.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6723.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6723.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6723.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6723.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6723.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6723.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6723.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6723.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6723.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6723.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6723.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6723.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6724.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6724.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6724.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6724.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6724.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6724.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6724.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6724.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6724.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6724.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6724.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6724.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6724.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6724.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6724.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6724.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6724.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6724.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6724.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6724.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6724.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6724.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6724.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6724.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6724.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6724.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6724.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6724.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6724.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6724.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6724.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6724.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6724.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6724.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6724.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6724.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6724.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6724.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6724.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6724.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6724.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6724.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6724.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6724.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6724.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6724.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6724.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6724.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6725.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6725.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6725.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6725.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6725.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6725.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6725.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6725.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6725.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6725.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6725.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6725.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6725.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6725.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6725.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6725.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6725.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6725.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6725.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6725.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6725.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6725.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6725.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6725.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6725.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6725.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6725.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6725.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6725.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6725.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6725.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6725.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6725.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6725.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6725.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6725.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6725.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6725.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6725.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6725.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6725.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6725.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6725.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6725.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6725.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6725.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6725.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6725.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6726.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6726.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6726.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6726.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6726.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6726.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6726.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6726.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6726.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6726.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6726.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6726.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6726.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6726.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6726.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6726.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6726.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6726.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6726.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6726.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6726.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6726.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6726.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6726.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6726.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6726.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6726.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6726.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6726.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6726.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6726.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6726.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6726.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6726.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6726.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6726.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6726.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6726.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6726.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6726.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6726.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6726.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6726.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6726.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6726.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6726.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6726.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6726.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6727.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6727.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6727.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6727.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6727.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6727.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6727.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6727.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6727.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6727.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6727.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6727.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6727.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6727.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6727.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6727.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6727.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6727.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6727.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6727.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6727.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6727.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6727.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6727.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6727.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6727.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6727.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6727.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6727.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6727.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6727.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6727.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6727.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6727.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6727.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6727.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6727.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6727.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6727.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6727.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6727.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6727.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6727.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6727.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6727.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6727.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6727.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6727.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6728.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6728.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6728.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6728.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6728.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6728.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6728.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6728.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6728.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6728.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6728.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6728.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6728.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6728.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6728.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6728.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6728.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6728.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6728.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6729.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6729.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6729.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6729.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6729.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6729.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6729.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6729.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6729.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6729.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6729.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6729.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6729.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6729.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6729.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6729.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6729.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6729.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6729.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6729.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6729.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6729.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6729.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6729.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6729.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6729.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6729.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6729.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6729.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6729.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6729.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6730.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6730.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6730.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6730.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6730.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6730.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6730.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6730.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6730.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6730.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6730.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6730.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6730.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6730.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6730.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6730.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6730.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6730.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6730.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6730.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6730.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6730.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6730.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6730.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6730.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6730.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6730.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6730.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6730.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6730.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6730.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6730.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6730.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6730.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6730.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6730.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6730.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6730.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6730.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6730.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6730.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6730.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6730.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6730.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6730.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6730.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6730.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6730.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6731.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6731.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6731.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6731.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6731.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6731.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6731.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6731.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6731.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6731.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6731.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6731.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6731.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6731.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6731.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6731.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6731.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6731.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6731.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6731.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6731.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6731.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6731.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6731.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6731.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6731.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6731.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6732.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6732.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6732.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6732.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6732.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6732.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6732.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6732.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6732.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6732.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6732.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6732.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6732.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6732.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6732.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6732.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6732.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6732.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6732.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6732.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6732.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6732.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6732.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6732.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6732.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6732.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6732.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6732.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6732.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6732.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6732.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6732.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6732.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6732.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6732.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6732.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6732.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6732.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6732.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6732.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6732.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6732.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6732.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6732.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6732.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6732.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6732.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6732.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6732.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6733.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6733.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6733.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6733.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6733.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6733.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6733.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6733.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6733.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6733.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6733.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6733.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6733.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6733.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6733.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6733.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6733.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6733.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6733.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6733.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6733.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6733.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6733.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6733.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6733.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6733.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6733.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6733.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6733.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6733.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6733.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6733.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6733.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6733.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6733.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6733.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6733.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6733.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6733.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6733.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6733.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6733.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6733.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6733.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6733.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6733.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6733.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6733.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6734.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6734.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6734.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6734.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6734.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6734.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6734.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6734.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6734.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6734.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6734.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6734.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6734.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6734.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6734.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6734.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6734.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6734.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6734.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6734.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6734.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6734.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6734.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6734.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6734.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6734.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6734.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6734.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6734.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6734.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6734.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6734.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6734.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6734.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6734.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6734.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6734.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6734.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6734.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6734.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6734.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6734.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6734.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6734.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6734.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6734.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6734.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6734.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6735.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6735.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6735.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6735.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6735.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6735.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6735.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6735.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6735.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6735.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6735.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6735.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6735.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6735.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6735.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6735.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6735.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6735.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6735.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6735.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6735.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6735.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6735.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6735.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6735.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6735.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6735.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6735.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6735.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6735.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6735.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6735.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6735.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6735.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6735.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6735.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6735.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6735.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6735.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6735.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6735.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6735.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6735.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6735.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6735.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6735.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6735.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6735.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6736.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6736.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6736.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6736.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6736.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6736.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6736.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6736.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6736.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6736.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6736.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6736.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6736.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6736.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6736.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6736.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6736.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6736.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6736.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6736.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6736.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6736.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6736.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6736.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6736.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6736.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6736.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6736.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6736.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6736.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6736.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6736.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6736.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6736.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6736.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6736.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6736.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6736.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6736.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6736.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6736.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6736.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6736.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6736.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6736.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6736.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6736.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6737.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6737.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6737.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6737.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6737.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6737.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6737.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6737.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6737.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6737.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6737.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6737.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6737.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6737.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6737.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6737.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6737.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6737.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6737.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6737.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6737.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6737.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6737.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6737.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6737.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6737.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6737.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6737.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6737.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6737.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6737.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6737.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6737.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6737.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6737.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6737.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6737.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6737.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6737.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6737.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6737.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6737.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6737.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6737.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6737.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6737.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6737.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6738.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6738.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6738.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6738.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6738.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6738.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6738.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6738.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6738.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6738.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6738.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6738.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6738.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6738.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6738.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6738.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6738.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6738.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6738.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6738.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6738.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6738.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6738.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6738.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6738.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6738.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6738.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6738.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6738.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6738.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6738.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6738.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6738.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6738.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6738.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6738.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6738.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6738.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6738.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6738.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6738.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6738.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6738.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6738.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6738.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6738.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6738.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6738.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6739.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6739.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6739.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6739.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6739.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6739.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6739.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6739.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6739.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6739.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6739.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6739.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6739.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6739.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6739.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6739.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6739.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6739.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6739.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6739.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6739.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6739.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6739.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6739.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6739.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6739.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6739.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6739.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6739.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6739.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6739.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6739.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6739.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6739.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6739.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6739.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6739.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6739.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6739.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6739.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6739.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6739.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6739.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6739.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6739.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6739.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6739.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6739.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6740.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6740.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6740.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6740.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6740.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6740.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6740.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6740.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6740.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6740.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6740.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6740.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6740.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6740.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6740.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6740.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6740.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6740.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6740.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6740.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6740.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6740.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6740.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6740.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6740.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6740.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6740.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6740.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6740.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6740.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6740.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6740.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6740.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6740.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6740.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6740.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6740.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6740.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6740.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6740.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6740.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6740.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6740.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6740.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6740.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6740.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6740.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6740.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6741.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6741.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6741.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6741.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6741.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6741.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6741.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6741.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6741.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6741.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6741.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6741.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6741.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6741.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6741.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6741.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6741.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6741.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6741.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6741.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6741.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6741.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6741.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6741.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6741.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6741.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6741.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6741.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6741.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6741.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6741.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6741.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6741.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6741.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6741.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6741.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6741.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6741.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6741.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6741.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6741.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6741.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6741.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6741.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6741.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6741.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6742.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6742.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6742.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6742.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6742.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6742.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6742.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6742.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6742.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6742.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6742.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6742.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6742.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6742.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6742.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6742.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6742.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6742.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6742.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6742.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6742.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6742.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6742.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6742.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6742.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6742.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6742.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6742.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6742.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6742.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6742.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6742.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6742.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6742.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6742.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6742.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6742.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6742.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6742.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6742.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6742.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6742.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6742.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6742.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6742.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6742.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6742.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6742.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6743.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6743.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6743.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6743.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6743.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6743.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6743.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6743.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6743.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6743.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6743.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6743.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6743.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6743.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6743.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6743.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6743.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6743.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6743.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6743.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6743.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6743.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6743.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6743.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6743.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6743.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6743.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6743.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6743.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6743.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6743.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6743.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6743.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6743.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6743.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6743.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6743.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6743.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6743.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6743.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6743.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6743.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6743.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6743.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6743.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6743.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6743.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6743.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6744.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6744.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6744.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6744.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6744.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6744.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6744.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6744.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6744.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6744.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6744.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6744.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6744.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6744.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6744.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6744.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6744.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6744.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6744.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6744.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6744.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6744.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6744.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6744.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6744.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6744.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6744.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6744.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6744.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6744.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6744.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6744.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6744.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6744.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6744.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6744.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6744.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6744.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6744.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6744.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6744.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6744.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6744.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6744.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6744.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6744.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6744.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6745.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6745.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6745.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6745.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6745.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6745.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6745.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6745.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6745.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6745.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6745.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6745.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6745.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6745.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6745.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6745.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6745.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6745.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6745.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6745.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6745.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6745.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6745.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6745.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6745.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6745.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6745.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6745.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6745.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6745.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6745.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6745.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6745.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6745.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6745.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6745.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6745.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6745.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6745.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6745.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6745.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6745.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6745.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6745.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6745.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6745.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6745.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6745.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6745.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6746.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6746.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6746.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6746.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6746.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6746.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6746.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6746.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6746.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6746.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6746.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6746.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6746.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6746.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6746.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6746.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6746.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6746.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6746.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6746.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6746.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6746.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6746.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6746.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6746.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6746.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6746.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6746.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6746.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6746.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6746.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6746.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6746.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6746.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6746.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6746.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6746.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6746.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6746.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6746.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6746.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6746.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6746.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6746.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6746.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6746.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6746.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6747.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6747.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6747.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6747.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6747.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6747.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6747.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6747.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6747.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6747.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6747.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6747.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6747.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6747.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6747.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6747.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6747.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6747.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6747.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6747.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6747.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6747.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6747.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6747.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6747.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6747.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6747.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6747.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6747.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6747.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6747.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6747.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6747.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6747.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6747.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6747.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6747.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6747.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6747.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6747.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6747.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6747.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6747.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6747.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6747.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6747.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6747.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6748.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6748.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6748.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6748.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6748.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6748.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6748.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6748.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6748.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6748.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6748.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6748.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6748.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6748.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6748.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6748.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6748.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6748.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6748.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6748.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6748.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6748.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6748.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6748.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6748.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6748.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6748.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6748.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6748.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6748.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6749.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6749.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6749.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6749.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6749.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6749.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6749.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6749.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6749.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6749.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6749.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6749.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6749.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6749.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6749.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6749.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6749.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6749.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6749.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6749.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6749.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6749.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6749.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6749.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6749.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6749.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6749.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6749.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6749.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6749.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6749.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6749.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6749.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6749.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6749.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6749.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6749.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6749.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6749.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6749.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6749.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6749.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6749.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6749.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6749.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6749.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6749.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6749.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6749.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6750.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6750.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6750.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6750.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6750.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6750.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6750.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6750.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6750.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6750.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6750.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6750.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6750.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6750.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6750.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6750.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6750.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6750.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6750.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6750.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6750.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6750.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6750.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6750.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6750.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6750.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6750.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6750.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6750.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6750.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6750.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6750.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6750.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6750.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6750.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6750.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6750.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6750.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6750.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6750.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6750.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6750.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6750.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6750.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6750.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6750.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6750.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6750.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6751.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6751.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6751.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6751.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6751.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6751.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6751.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6751.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6751.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6751.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6751.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6751.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6751.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6751.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6751.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6751.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6751.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6751.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6751.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6751.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6751.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6751.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6751.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6751.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6751.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6751.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6751.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6751.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6751.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6751.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6751.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6751.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6751.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6751.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6751.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6751.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6751.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6751.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6751.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6751.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6751.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6751.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6751.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6751.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6751.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6751.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6751.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6751.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6751.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6751.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6752.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6752.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6752.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6752.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6752.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6752.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6752.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6752.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6752.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6752.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6752.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6752.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6752.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6752.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6752.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6752.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6752.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6752.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6752.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6752.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6752.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6752.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6752.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6752.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6752.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6752.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6752.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6752.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6752.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6752.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6752.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6752.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6752.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6752.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6752.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6752.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6752.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6752.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6752.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6752.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6752.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6752.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6752.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6752.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6752.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6752.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6752.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6752.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6753.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6753.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6753.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6753.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6753.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6753.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6753.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6753.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6753.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6753.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6753.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6753.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6753.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6753.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6753.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6753.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6753.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6753.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6753.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6753.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6753.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6753.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6753.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6753.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6753.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6753.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6753.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6753.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6753.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6753.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6753.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6753.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6753.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6753.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6753.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6753.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6753.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6753.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6753.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6753.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6753.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6753.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6753.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6753.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6753.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6753.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6753.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6753.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6754.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6754.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6754.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6754.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6754.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6754.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6754.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6754.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6754.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6754.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6754.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6754.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6754.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6754.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6754.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6754.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6754.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6754.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6754.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6754.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6754.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6754.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6754.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6754.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6754.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6754.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6754.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6754.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6754.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6754.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6754.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6754.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6754.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6754.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6754.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6754.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6754.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6754.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6754.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6754.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6754.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6754.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6754.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6754.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6754.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6754.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6754.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6754.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6755.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6755.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6755.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6755.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6755.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6755.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6755.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6755.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6755.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6755.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6755.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6755.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6755.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6755.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6755.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6755.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6755.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6755.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6755.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6755.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6755.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6755.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6755.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6755.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6755.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6755.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6755.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6755.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6755.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6755.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6755.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6755.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6755.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6755.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6755.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6755.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6755.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6755.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6755.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6755.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6755.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6755.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6755.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6755.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6755.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6755.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6755.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6755.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6756.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6756.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6756.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6756.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6756.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6756.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6756.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6756.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6756.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6756.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6756.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6756.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6756.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6756.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6756.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6756.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6756.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6756.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6756.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6756.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6756.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6756.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6756.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6756.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6756.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6756.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6756.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6756.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6756.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6756.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6756.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6756.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6756.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6756.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6756.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6756.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6756.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6756.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6756.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6756.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6756.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6756.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6756.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6756.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6756.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6756.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6756.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6756.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6756.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6756.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6757.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6757.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6757.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6757.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6757.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6757.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6757.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6757.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6757.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6757.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6757.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6757.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6757.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6757.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6757.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6757.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6757.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6757.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6757.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6757.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6757.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6757.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6757.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6757.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6757.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6757.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6757.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6757.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6757.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6757.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6757.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6757.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6757.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6757.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6757.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6757.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6757.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6757.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6757.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6757.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6757.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6757.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6757.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6757.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6757.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6757.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6757.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6757.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6758.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6758.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6758.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6758.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6758.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6758.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6758.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6758.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6758.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6758.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6758.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6758.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6758.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6758.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6758.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6758.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6758.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6758.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6758.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6758.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6758.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6758.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6758.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6758.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6758.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6758.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6758.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6758.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6758.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6758.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6758.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6758.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6758.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6758.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6758.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6758.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6758.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6758.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6758.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6758.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6758.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6758.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6758.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6758.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6758.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6758.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6758.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6758.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6759.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6759.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6759.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6759.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6759.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6759.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6759.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6759.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6759.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6759.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6759.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6759.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6759.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6759.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6759.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6759.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6759.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6759.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6759.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6759.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6759.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6759.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6759.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6759.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6759.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6759.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6759.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6759.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6759.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6759.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6759.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6759.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6759.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6759.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6759.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6759.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6759.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6759.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6759.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6759.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6759.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6759.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6759.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6759.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6759.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6759.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6759.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6759.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6760.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6760.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6760.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6760.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6760.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6760.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6760.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6760.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6760.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6760.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6760.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6760.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6760.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6760.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6760.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6760.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6760.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6760.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6760.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6760.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6760.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6760.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6760.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6760.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6760.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6760.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6760.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6760.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6760.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6760.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6760.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6760.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6760.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6760.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6760.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6760.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6760.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6760.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6760.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6760.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6760.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6760.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6760.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6760.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6760.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6760.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6760.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6760.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6761.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6761.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6761.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6761.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6761.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6761.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6761.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6761.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6761.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6761.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6761.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6761.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6761.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6761.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6761.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6761.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6761.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6761.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6761.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6761.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6761.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6761.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6761.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6761.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6761.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6761.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6761.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6761.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6761.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6761.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6761.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6761.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6762.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6762.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6762.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6762.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6762.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6762.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6762.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6762.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6762.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6762.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6762.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6762.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6762.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6762.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6762.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6762.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6762.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6762.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6762.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6762.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6762.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6762.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6762.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6762.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6762.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6762.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6762.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6762.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6762.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6762.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6762.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6762.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6762.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6762.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6762.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6762.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6762.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6762.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6762.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6762.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6762.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6762.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6762.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6762.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6762.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6762.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6762.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6762.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6763.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6763.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6763.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6763.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6763.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6763.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6763.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6763.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6763.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6763.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6763.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6763.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6763.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6763.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6763.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6763.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6763.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6763.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6763.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6763.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6763.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6763.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6763.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6763.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6763.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6763.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6763.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6763.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6763.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6763.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6763.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6763.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6763.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6763.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6763.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6763.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6763.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6763.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6763.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6763.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6763.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6763.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6763.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6763.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6763.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6763.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6763.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6763.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6764.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6764.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6764.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6764.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6764.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6764.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6764.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6764.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6764.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6764.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6764.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6764.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6764.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6764.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6764.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6764.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6764.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6764.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6764.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6764.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6764.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6764.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6764.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6764.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6765.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6765.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6765.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6765.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6766.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6766.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6766.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6766.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6766.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6766.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6766.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6766.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6766.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6766.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6766.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6766.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6766.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6766.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6766.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6766.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6767.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6767.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6767.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6767.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6768.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6768.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6768.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6768.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6768.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6768.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6768.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6768.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6768.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6768.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6768.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6768.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6768.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6768.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6768.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6768.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6768.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6768.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6768.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6768.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6768.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6768.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6768.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6768.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6768.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6768.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6768.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6768.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6768.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6768.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6768.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6768.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6768.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6768.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6768.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6768.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6768.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6768.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6768.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6768.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6768.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6768.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6768.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6768.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6768.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6768.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6768.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6768.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6769.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6769.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6769.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6769.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6769.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6769.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6769.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6769.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6769.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6769.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6769.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6769.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6769.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6769.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6769.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6769.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6769.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6769.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6769.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6769.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6769.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6769.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6769.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6769.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6769.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6769.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6769.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6769.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6769.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6769.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6769.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6769.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6769.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6769.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6769.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6769.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6769.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6769.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6769.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6769.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6769.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6769.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6769.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6769.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6769.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6769.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6769.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6769.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6770.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6770.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6770.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6770.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6770.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6770.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6770.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6770.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6770.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6770.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6770.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6770.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6770.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6770.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6770.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6770.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6770.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6770.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6770.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6770.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6770.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6770.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6770.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6770.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6770.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6770.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6770.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6770.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6770.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6770.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6770.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6770.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6770.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6770.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6770.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6770.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6770.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6770.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6770.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6770.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6770.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6770.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6770.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6770.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6770.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6770.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6770.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6770.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6771.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6771.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6771.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6771.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6771.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6771.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6771.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6771.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6771.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6771.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6771.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6771.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6771.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6771.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6771.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6771.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6771.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6771.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6771.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6771.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6771.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6771.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6771.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6771.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6771.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6771.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6771.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6771.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6771.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6771.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6771.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6771.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6771.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6771.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6771.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6771.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6771.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6771.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6771.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6771.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6771.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6771.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6771.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6771.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6771.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6771.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6771.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6771.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6772.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6772.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6772.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6772.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6772.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6772.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6772.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6772.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6772.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6772.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6772.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6772.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6772.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6772.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6772.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6772.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6772.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6772.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6772.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6772.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6772.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6772.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6772.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6772.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6772.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6772.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6772.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6772.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6772.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6772.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6772.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6772.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6772.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6772.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6772.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6772.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6772.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6772.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6772.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6772.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6772.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6772.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6772.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6772.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6772.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6772.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6772.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6772.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6773.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6773.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6773.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6773.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6773.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6773.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6773.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6773.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6773.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6773.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6773.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6773.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6773.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6773.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6773.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6773.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6773.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6773.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6773.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6773.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6773.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6773.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6773.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6773.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6773.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6773.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6773.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6773.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6773.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6773.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6773.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6773.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6773.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6773.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6773.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6773.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6773.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6773.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6773.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6773.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6773.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6773.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6773.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6773.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6773.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6773.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6773.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6773.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6773.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6774.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6774.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6774.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6774.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6774.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6774.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6774.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6774.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6774.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6774.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6774.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6774.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6774.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6774.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6774.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6774.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6774.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6774.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6774.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6774.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6774.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6774.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6774.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6774.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6774.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6774.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6774.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6774.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6774.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6774.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6774.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6774.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6774.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6774.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6774.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6774.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6774.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6774.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6774.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6774.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6774.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6774.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6774.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6774.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6774.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6774.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6774.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6775.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6775.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6775.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6775.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6775.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6775.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6775.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6775.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6775.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6775.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6775.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6775.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6775.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6775.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6775.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6775.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6775.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6775.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6775.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6775.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6775.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6775.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6775.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6775.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6775.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6775.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6775.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6775.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6775.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6775.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6775.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6775.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6775.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6775.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6775.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6775.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6775.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6775.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6775.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6775.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6775.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6775.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6775.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6775.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6775.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6775.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6775.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6775.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6776.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6776.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6776.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6776.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6776.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6776.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6776.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6776.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6776.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6776.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6776.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6776.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6776.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6776.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6776.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6776.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6776.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6776.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6776.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6776.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6776.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6776.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6776.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6776.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6776.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6776.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6776.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6776.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6776.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6776.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6776.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6777.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6777.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6777.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6777.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6777.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6777.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6777.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6777.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6777.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6777.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6777.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6777.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6777.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6777.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6777.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6777.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6777.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6777.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6777.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6777.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6777.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6777.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6777.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6777.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6777.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6777.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6777.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6777.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6777.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6777.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6777.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6777.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6777.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6777.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6777.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6777.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6777.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6777.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6777.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6777.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6777.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6777.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6777.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6777.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6777.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6777.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6777.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6778.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6778.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6778.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6778.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6778.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6778.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6778.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6778.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6778.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6778.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6778.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6778.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6778.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6778.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6778.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6778.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6778.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6778.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6778.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6778.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6778.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6778.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6778.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6778.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6778.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6778.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6778.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6778.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6778.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6778.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6778.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6778.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6778.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6778.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6778.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6778.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6778.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6778.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6778.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6778.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6778.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6778.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6778.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6778.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6778.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6778.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6778.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6778.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6779.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6779.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6779.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6779.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6779.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6779.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6779.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6779.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6779.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6779.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6779.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6779.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6779.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6779.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6779.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6779.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6779.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6779.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6779.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6779.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6779.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6779.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6779.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6779.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6779.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6779.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6779.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6779.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6779.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6779.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6779.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6779.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6779.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6779.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6779.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6779.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6779.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6779.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6779.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6779.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6779.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6779.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6779.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6779.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6779.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6779.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6779.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6779.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6780.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6780.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6780.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6780.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6780.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6780.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6780.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6780.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6780.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6780.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6780.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6780.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6780.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6780.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6780.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6780.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6780.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6780.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6780.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6780.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6780.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6780.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6780.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6780.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6780.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6780.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6780.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6780.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6780.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6780.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6780.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6780.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6780.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6780.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6780.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6780.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6780.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6780.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6780.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6780.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6780.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6780.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6780.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6780.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6780.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6780.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6780.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6780.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6780.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6780.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6781.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6781.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6781.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6781.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6781.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6781.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6781.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6781.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6781.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6781.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6781.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6781.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6781.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6781.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6781.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6781.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6781.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6781.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6781.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6781.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6781.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6781.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6781.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6781.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6781.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6781.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6781.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6781.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6781.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6781.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6781.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6781.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6781.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6781.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6781.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6781.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6781.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6781.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6781.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6781.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6781.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6781.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6781.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6781.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6781.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6781.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6781.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6781.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6782.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6782.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6782.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6782.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6782.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6782.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6782.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6782.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6782.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6782.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6782.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6782.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6782.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6782.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6782.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6782.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6782.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6782.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6782.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6782.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6782.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6782.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6782.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6782.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6782.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6782.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6782.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6782.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6782.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6782.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6782.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6782.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6783.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6783.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6783.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6783.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6783.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6783.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6783.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6783.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6783.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6783.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6783.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6783.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6783.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6783.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6783.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6783.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6783.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6783.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6783.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6783.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6783.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6783.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6783.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6783.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6783.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6783.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6783.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6783.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6783.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6783.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6783.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6783.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6783.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6783.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6783.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6783.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6783.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6783.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6783.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6783.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6783.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6783.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6783.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6783.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6783.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6783.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6783.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6783.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6784.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6784.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6784.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6784.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6784.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6784.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6784.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6784.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6784.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6784.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6784.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6784.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6784.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6784.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6784.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6784.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6784.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6784.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6784.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6784.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6784.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6784.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6784.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6784.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6784.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6784.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6784.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6784.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6784.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6784.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6784.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6784.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6784.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6784.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6784.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6784.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6784.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6784.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6784.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6784.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6784.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6784.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6784.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6784.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6784.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6784.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6784.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6784.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6784.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6785.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6785.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6785.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6785.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6785.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6785.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6785.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6785.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6785.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6785.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6785.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6785.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6785.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6785.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6785.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6785.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6785.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6785.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6785.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6785.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6785.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6785.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6785.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6785.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6785.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6785.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6785.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6785.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6785.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6785.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6785.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6785.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6785.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6785.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6785.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6785.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6785.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6785.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6785.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6785.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6785.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6785.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6785.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6785.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6785.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6785.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6785.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6785.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6785.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6786.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6786.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6786.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6786.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6786.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6786.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6786.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6786.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6786.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6786.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6786.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6786.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6786.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6786.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6786.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6786.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6786.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6786.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6786.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6786.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6786.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6786.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6786.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6786.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6786.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6786.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6786.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6786.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6786.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6786.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6786.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6786.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6786.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6786.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6786.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6786.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6786.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6786.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6786.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6786.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6786.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6786.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6786.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6786.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6786.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6786.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6786.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6786.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6786.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6787.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6787.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6787.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6787.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6787.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6787.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6787.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6787.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6787.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6787.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6787.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6787.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6787.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6787.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6787.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6787.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6787.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6787.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6787.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6787.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6787.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6787.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6787.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6787.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6787.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6787.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6787.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6787.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6787.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6787.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6787.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6787.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6787.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6787.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6787.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6787.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6787.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6787.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6787.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6787.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6787.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6787.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6787.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6787.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6787.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6787.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6787.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6787.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6787.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6788.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6788.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6788.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6788.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6788.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6788.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6788.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6788.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6788.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6788.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6788.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6788.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6788.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6788.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6788.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6788.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6788.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6788.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6788.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6788.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6788.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6788.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6788.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6788.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6788.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6788.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6788.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6788.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6788.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6788.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6788.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6788.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6788.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6788.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6788.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6788.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6788.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6788.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6788.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6788.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6788.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6788.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6788.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6788.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6788.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6788.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6788.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6788.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6789.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6789.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6789.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6789.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6789.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6789.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6789.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6789.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6789.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6789.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6789.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6789.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6789.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6789.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6789.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6789.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6789.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6789.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6789.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6789.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6789.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6789.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6789.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6789.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6789.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6789.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6789.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6789.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6789.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6789.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6789.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6789.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6789.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6789.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6789.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6789.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6789.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6789.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6789.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6789.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6789.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6789.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6789.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6789.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6789.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6789.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6789.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6789.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6790.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6790.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6790.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6790.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6790.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6790.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6790.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6790.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6790.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6790.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6790.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6790.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6790.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6790.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6790.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6790.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6790.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6790.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6790.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6790.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6790.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6790.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6790.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6790.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6790.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6790.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6790.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6790.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6790.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6790.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6790.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6790.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6790.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6790.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6790.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6790.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6790.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6790.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6790.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6790.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6790.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6790.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6790.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6790.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6790.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6790.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6790.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6790.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6791.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6791.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6791.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6791.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6792.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6792.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6792.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6792.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6792.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6792.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6792.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6792.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6792.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6792.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6792.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6792.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6792.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6792.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6792.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6792.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6792.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6792.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6792.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6792.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6792.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6792.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6792.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6792.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6792.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6792.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6792.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6792.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6792.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6792.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6792.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6792.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6792.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6792.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6792.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6792.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6792.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6792.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6792.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6792.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6792.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6792.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6792.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6792.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6792.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6792.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6792.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6792.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6793.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6793.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6793.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6793.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6793.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6793.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6793.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6793.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6793.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6793.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6793.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6793.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6793.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6793.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6793.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6793.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6793.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6793.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6793.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6793.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6793.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6793.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6793.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6793.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6793.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6793.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6793.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6793.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6793.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6793.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6793.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6793.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6793.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6793.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6793.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6793.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6793.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6793.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6793.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6793.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6793.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6793.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6793.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6793.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6793.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6793.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6793.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6794.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6794.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6794.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6794.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6794.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6794.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6794.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6794.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6794.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6794.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6794.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6794.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6794.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6794.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6794.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6794.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6794.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6794.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6794.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6794.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6794.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6794.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6794.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6794.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6794.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6794.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6794.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6794.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6794.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6794.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6794.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6794.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6794.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6794.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6794.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6794.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6794.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6794.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6794.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6794.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6794.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6794.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6794.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6794.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6794.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6794.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6794.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6795.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6795.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6795.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6795.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6795.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6795.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6795.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6795.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6795.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6795.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6795.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6795.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6795.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6795.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6795.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6795.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6795.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6795.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6795.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6795.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6795.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6795.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6795.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6795.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6795.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6795.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6795.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6795.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6795.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6795.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6795.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6795.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6795.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6795.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6795.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6795.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6795.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6795.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6795.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6795.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6795.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6795.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6795.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6795.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6795.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6795.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6796.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6796.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6796.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6796.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6796.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6796.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6796.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6796.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6796.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6796.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6796.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6796.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6796.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6796.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6796.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6796.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6796.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6796.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6796.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6796.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6796.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6796.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6796.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6796.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6796.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6796.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6796.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6796.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6796.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6796.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6796.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6796.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6796.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6796.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6796.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6796.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6796.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6796.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6796.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6796.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6796.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6796.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6796.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6796.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6796.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6796.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6796.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6796.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6797.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6797.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6797.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6797.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6797.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6797.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6797.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6797.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6797.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6797.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6797.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6797.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6797.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6797.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6797.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6797.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6797.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6797.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6797.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6797.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6797.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6797.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6797.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6797.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6797.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6797.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6797.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6797.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6797.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6797.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6797.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6797.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6797.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6797.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6797.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6797.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6797.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6797.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6797.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6797.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6797.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6797.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6797.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6797.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6797.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6797.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6797.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6798.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6798.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6798.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6798.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6798.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6798.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6798.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6798.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6798.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6798.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6798.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6798.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6798.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6798.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6798.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6798.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6798.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6799.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6799.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6799.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6799.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6799.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6799.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6799.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6799.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6799.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6799.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6799.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6799.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6799.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6799.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6799.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6799.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6799.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6799.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6799.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6799.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6799.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6799.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6799.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6799.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6799.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6799.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6799.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6799.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6799.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6799.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6799.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6799.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6799.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6799.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6799.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6799.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6799.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6799.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6799.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6799.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6799.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6799.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6799.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6799.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6799.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6799.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6799.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6799.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6800.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6800.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6800.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6800.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6800.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6800.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6800.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6800.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6800.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6800.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6800.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6800.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6800.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6800.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6800.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6800.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6800.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6800.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6800.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6800.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6800.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6800.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6800.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6800.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6800.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6800.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6800.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6800.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6800.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6800.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6800.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6800.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6800.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6800.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6800.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6800.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6800.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6800.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6800.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6800.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6800.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6800.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6800.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6800.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6800.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6800.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6800.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6801.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6801.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6801.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6801.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6801.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6801.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6801.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6801.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6801.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6801.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6801.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6801.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6801.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6801.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6801.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6801.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6801.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6801.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6801.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6801.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6801.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6801.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6801.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6801.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6801.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6801.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6801.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6801.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6801.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6801.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6801.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6801.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6801.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6801.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6801.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6801.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6801.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6801.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6801.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6801.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6801.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6801.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6801.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6801.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6801.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6801.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6801.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6801.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6801.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6802.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6802.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6802.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6802.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6802.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6802.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6802.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6802.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6802.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6802.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6802.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6802.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6802.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6802.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6802.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6802.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6802.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6802.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6802.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6802.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6802.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6802.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6802.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6802.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6802.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6802.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6802.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6802.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6802.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6802.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6802.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6802.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6802.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6802.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6802.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6802.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6802.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6802.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6802.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6802.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6802.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6802.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6802.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6802.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6802.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6802.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6802.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6803.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6803.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6803.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6803.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6803.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6803.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6803.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6803.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6803.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6803.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6803.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6803.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6803.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6803.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6803.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6803.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6803.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6803.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6803.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6803.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6803.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6803.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6803.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6803.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6803.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6803.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6803.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6803.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6804.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6804.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6804.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6804.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6804.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6804.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6804.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6804.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6804.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6804.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6804.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6804.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6804.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6804.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6804.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6804.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6805.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6805.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6805.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6805.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6805.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6805.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6805.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6805.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6805.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6805.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6805.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6805.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6805.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6806.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6806.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6806.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6806.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6806.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6806.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6806.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6806.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6806.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6806.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6806.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6806.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6806.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6806.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6806.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6806.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6806.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6806.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6806.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6806.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6806.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6806.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6806.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6806.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6806.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6806.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6806.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6806.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6806.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6806.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6806.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6806.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6806.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6806.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6806.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6806.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6806.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6806.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6806.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6806.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6806.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6806.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6806.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6806.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6806.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6806.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6806.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6806.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6807.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6807.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6807.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6807.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6807.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6807.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6807.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6807.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6807.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6807.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6807.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6807.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6807.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6807.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6807.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6807.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6807.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6807.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6807.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6807.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6807.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6807.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6807.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6807.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6807.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6807.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6807.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6807.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6807.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6807.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6807.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6807.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6807.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6807.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6807.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6807.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6807.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6807.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6807.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6807.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6807.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6807.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6807.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6807.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6807.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6807.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6807.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6807.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6808.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6808.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6808.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6808.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6808.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6808.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6808.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6808.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6808.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6808.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6808.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6808.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6808.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6808.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6808.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6808.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6808.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6808.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6808.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6808.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6808.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6808.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6808.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6808.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6808.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6808.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6808.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6808.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6808.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6808.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6808.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6808.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6808.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6808.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6808.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6808.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6808.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6808.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6808.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6808.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6808.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6808.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6808.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6808.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6808.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6808.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6808.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6809.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6809.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6809.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6809.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6809.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6809.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6809.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6809.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6809.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6809.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6809.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6809.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6809.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6809.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6809.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6809.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6809.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6809.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6809.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6809.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6809.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6809.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6809.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6809.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6809.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6809.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6809.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6809.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6809.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6810.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6810.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6810.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6810.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6810.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6810.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6810.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6810.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6810.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6810.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6810.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6810.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6810.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6810.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6810.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6810.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6810.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6810.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6810.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6810.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6810.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6810.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6810.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6810.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6810.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6810.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6810.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6810.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6810.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6810.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6810.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6810.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6810.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6810.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6810.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6810.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6810.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6810.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6810.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6810.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6810.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6810.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6810.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6810.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6810.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6810.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6810.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6810.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6811.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6811.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6811.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6811.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6811.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6811.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6811.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6811.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6811.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6811.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6811.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6811.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6811.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6811.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6811.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6811.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6811.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6811.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6811.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6811.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6811.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6811.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6811.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6811.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6811.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6811.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6811.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6811.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6811.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6811.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6812.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6812.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6812.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6812.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6812.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6812.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6812.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6812.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6812.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6812.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6812.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6812.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6812.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6812.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6812.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6812.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6812.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6812.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6812.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6812.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6812.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6812.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6812.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6812.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6812.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6812.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6812.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6812.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6812.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6812.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6812.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6812.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6812.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6812.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6812.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6812.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6812.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6812.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6812.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6812.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6812.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6812.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6812.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6812.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6812.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6812.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6812.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6812.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6813.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6813.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6813.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6813.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6813.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6813.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6813.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6813.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6813.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6813.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6813.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6813.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6813.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6813.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6813.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6813.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6813.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6813.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6813.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6813.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6813.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6813.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6813.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6813.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6813.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6813.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6813.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6813.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6813.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6813.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6813.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6813.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6813.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6813.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6813.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6813.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6813.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6813.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6813.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6813.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6813.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6813.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6813.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6813.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6813.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6813.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6813.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6814.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6814.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6814.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6814.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6814.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6814.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6814.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6814.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6814.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6814.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6814.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6814.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6814.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6814.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6814.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6814.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6814.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6814.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6814.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6814.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6814.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6814.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6814.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6814.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6814.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6814.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6814.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6814.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6814.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6814.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6814.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6815.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6815.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6815.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6815.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6815.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6815.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6815.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6815.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6815.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6815.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6815.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6815.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6815.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6815.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6815.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6815.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6815.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6815.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6815.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6815.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6815.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6815.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6815.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6815.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6815.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6815.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6815.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6815.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6815.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6815.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6815.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6815.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6815.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6815.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6815.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6815.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6815.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6815.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6815.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6815.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6815.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6815.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6815.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6815.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6815.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6815.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6815.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6815.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6816.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6816.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6816.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6816.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6817.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6817.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6817.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6817.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6817.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6817.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6817.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6817.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6817.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6817.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6817.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6817.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6817.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6817.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6817.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6817.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6817.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6817.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6817.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6817.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6817.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6817.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6817.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6817.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6817.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6817.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6817.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6817.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6817.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6817.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6817.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6817.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6817.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6817.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6817.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6817.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6817.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6817.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6817.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6817.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6817.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6817.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6817.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6817.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6817.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6817.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6817.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6817.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6818.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6818.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6818.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6818.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6818.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6818.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6818.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6818.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6818.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6818.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6818.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6818.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6818.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6818.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6818.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6818.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6818.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6818.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6818.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6818.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6818.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6818.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6818.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6818.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6818.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6818.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6818.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6818.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6818.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6818.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6818.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6818.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6818.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6818.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6818.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6818.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6818.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6818.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6818.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6818.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6818.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6818.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6818.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6818.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6818.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6818.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6818.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6818.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6818.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6819.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6819.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6819.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6819.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6819.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6819.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6819.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6819.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6819.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6819.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6819.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6819.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6819.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6819.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6819.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6819.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6819.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6819.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6819.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6819.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6819.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6819.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6819.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6819.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6819.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6819.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6819.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6819.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6819.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6819.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6819.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6819.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6819.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6819.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6819.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6819.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6819.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6819.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6819.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6819.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6819.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6819.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6819.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6819.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6819.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6819.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6819.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6819.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6820.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6820.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6820.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6820.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6820.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6820.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6820.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6820.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6820.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6820.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6820.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6820.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6820.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6820.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6820.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6820.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6820.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6820.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6820.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6820.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6820.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6820.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6820.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6820.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6820.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6820.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6820.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6820.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6820.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6820.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6820.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6820.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6820.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6820.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6820.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6820.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6820.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6820.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6820.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6820.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6820.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6820.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6820.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6820.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6820.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6820.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6820.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6821.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6821.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6821.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6821.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6821.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6821.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6821.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6821.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6821.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6821.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6821.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6821.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6821.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6821.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6821.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6821.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6821.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6821.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6821.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6821.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6821.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6821.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6821.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6821.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6821.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6821.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6821.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6821.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6821.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6821.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6821.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6821.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6821.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6821.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6821.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6821.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6821.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6821.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6821.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6821.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6821.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6821.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6821.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6821.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6821.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6821.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6821.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6821.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6822.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6822.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6822.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6822.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6822.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6822.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6822.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6822.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6822.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6822.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6822.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6822.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6822.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6822.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6822.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6822.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6822.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6822.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6822.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6822.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6822.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6822.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6822.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6822.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6822.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6822.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6822.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6822.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6822.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6822.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6822.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6822.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6822.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6822.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6822.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6822.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6822.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6822.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6822.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6822.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6822.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6822.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6822.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6822.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6822.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6822.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6823.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6823.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6823.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6823.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6823.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6823.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6823.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6823.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6823.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6823.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6823.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6823.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6823.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6823.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6823.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6823.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6823.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6823.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6823.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6823.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6823.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6823.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6823.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6823.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6823.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6823.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6823.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6823.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6823.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6823.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6823.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6823.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6823.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6823.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6823.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6823.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6823.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6823.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6823.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6823.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6823.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6823.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6823.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6823.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6823.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6823.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6823.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6824.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6824.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6824.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6824.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6824.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6824.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6824.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6824.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6824.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6824.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6824.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6824.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6824.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6824.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6824.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6824.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6824.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6824.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6824.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6824.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6824.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6824.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6824.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6824.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6824.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6824.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6824.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6824.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6824.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6824.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6824.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6824.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6824.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6824.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6824.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6824.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6824.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6824.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6824.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6824.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6824.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6824.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6824.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6824.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6824.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6824.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6824.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6824.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6825.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6825.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6825.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6825.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6825.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6825.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6825.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6825.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6825.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6825.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6825.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6825.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6825.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6825.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6825.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6825.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6825.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6825.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6825.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6825.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6825.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6825.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6825.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6825.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6825.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6825.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6825.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6825.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6825.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6825.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6825.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6825.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6825.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6825.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6825.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6825.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6825.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6825.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6825.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6825.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6825.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6825.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6825.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6825.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6825.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6825.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6825.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6825.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6826.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6826.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6826.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6826.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6826.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6826.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6826.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6826.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6826.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6826.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6826.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6826.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6826.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6826.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6826.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6826.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6826.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6826.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6826.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6826.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6826.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6826.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6826.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6826.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6826.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6826.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6826.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6826.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6826.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6826.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6826.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6826.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6826.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6826.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6826.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6826.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6826.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6826.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6826.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6826.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6826.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6826.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6826.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6826.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6826.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6826.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6826.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6827.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6827.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6827.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6827.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6827.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6827.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6827.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6827.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6827.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6827.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6827.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6827.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6827.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6827.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6827.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6827.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6827.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6827.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6827.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6827.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6827.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6827.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6827.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6827.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6827.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6827.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6827.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6827.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6827.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6827.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6827.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6827.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6827.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6827.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6827.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6827.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6827.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6827.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6827.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6827.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6827.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6827.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6827.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6827.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6827.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6827.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6827.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6827.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6827.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6828.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6828.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6828.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6828.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6828.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6828.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6828.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6828.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6828.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6828.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6828.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6828.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6828.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6828.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6828.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6828.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6828.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6828.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6828.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6828.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6828.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6828.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6828.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6828.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6828.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6828.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6828.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6828.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6828.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6828.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6828.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6828.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6828.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6828.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6828.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6828.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6828.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6828.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6828.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6828.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6829.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6829.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6829.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6829.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6829.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6830.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6830.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6830.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6830.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6830.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6830.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6830.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6830.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6830.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6830.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6830.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6830.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6830.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6830.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6830.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6830.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6830.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6830.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6830.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6830.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6830.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6830.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6830.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6830.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6830.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6830.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6830.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6830.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6830.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6830.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6830.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6830.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6830.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6830.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6830.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6830.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6830.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6830.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6830.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6830.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6830.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6830.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6830.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6830.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6830.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6830.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6830.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6830.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6830.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6830.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6831.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6831.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6831.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6831.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6831.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6831.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6831.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6831.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6831.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6831.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6831.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6831.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6831.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6831.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6831.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6831.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6831.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6831.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6831.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6831.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6831.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6831.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6831.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6831.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6831.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6831.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6831.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6831.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6831.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6831.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6831.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6831.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6831.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6831.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6831.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6831.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6831.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6831.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6831.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6831.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6831.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6831.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6831.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6831.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6831.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6831.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6831.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6831.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6832.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6832.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6832.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6832.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6832.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6832.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6832.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6832.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6832.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6832.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6832.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6832.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6832.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6832.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6832.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6832.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6832.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6832.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6832.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6832.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6832.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6832.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6832.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6832.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6832.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6832.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6832.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6832.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6832.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6832.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6832.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6833.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6833.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6833.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6833.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6833.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6833.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6833.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6833.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6833.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6833.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6833.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6833.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6833.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6833.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6833.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6833.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6833.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6833.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6833.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6833.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6833.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6833.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6833.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6833.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6833.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6833.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6833.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6833.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6833.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6833.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6833.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6833.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6833.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6833.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6833.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6833.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6833.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6833.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6833.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6833.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6833.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6833.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6833.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6833.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6833.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6833.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6833.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6833.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6834.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6834.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6834.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6834.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6834.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6834.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6834.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6834.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6834.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6834.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6834.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6834.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6834.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6834.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6834.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6834.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6834.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6834.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6834.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6834.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6834.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6834.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6834.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6834.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6834.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6834.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6834.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6834.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6834.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6834.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6834.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6834.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6835.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6835.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6835.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6835.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6835.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6835.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6835.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6835.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6835.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6835.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6835.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6835.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6835.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6835.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6835.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6835.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6835.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6835.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6835.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6835.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6835.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6835.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6835.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6835.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6835.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6835.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6835.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6835.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6835.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6835.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6835.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6835.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6835.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6835.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6835.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6835.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6835.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6835.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6835.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6835.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6835.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6835.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6835.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6835.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6835.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6835.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6835.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6835.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6836.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6836.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6836.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6836.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6836.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6836.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6836.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6836.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6836.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6836.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6836.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6836.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6836.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6836.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6836.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6836.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6836.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6836.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6836.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6836.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6836.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6836.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6836.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6836.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6836.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6836.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6836.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6836.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6836.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6836.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6836.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6836.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6836.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6836.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6836.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6836.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6836.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6836.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6836.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6836.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6836.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6836.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6836.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6836.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6836.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6836.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6836.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6837.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6837.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6837.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6837.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6837.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6837.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6837.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6837.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6837.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6837.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6837.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6837.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6837.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6837.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6837.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6837.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6837.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6837.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6837.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6837.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6837.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6837.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6837.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6837.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6837.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6837.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6837.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6837.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6837.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6837.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6837.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6837.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6837.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6837.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6837.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6837.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6837.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6837.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6837.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6837.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6837.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6837.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6837.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6837.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6837.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6837.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6837.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6837.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6838.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6838.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6838.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6838.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6838.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6838.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6838.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6838.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6838.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6838.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6838.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6838.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6838.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6838.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6838.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6838.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6838.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6838.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6838.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6838.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6838.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6838.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6838.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6838.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6838.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6838.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6838.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6838.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6838.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6838.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6838.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6838.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6838.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6838.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6838.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6838.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6838.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6838.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6838.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6838.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6838.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6838.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6838.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6838.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6838.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6838.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6838.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6838.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6839.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6839.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6839.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6839.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6839.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6839.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6839.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6839.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6839.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6839.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6839.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6839.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6839.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6839.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6839.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6839.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6839.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6839.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6839.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6839.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6839.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6839.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6839.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6839.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6839.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6839.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6839.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6839.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6839.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6839.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6839.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6839.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6839.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6839.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6839.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6839.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6839.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6839.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6839.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6839.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6839.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6839.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6839.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6839.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6839.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6839.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6839.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6839.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6840.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6840.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6840.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6840.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6840.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6840.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6840.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6840.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6840.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6840.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6840.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6841.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6841.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6841.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6841.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6841.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6841.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6841.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6841.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6841.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6841.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6841.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6841.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6841.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6841.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6841.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6841.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6841.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6841.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6841.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6841.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6841.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6841.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6841.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6841.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6841.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6841.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6841.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6841.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6841.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6841.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6841.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6841.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6841.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6841.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6841.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6841.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6841.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6841.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6841.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6841.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6841.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6841.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6841.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6841.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6841.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6841.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6841.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6841.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6841.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6842.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6842.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6842.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6842.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6842.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6842.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6842.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6842.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6842.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6842.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6842.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6842.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6842.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6842.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6842.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6842.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6842.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6842.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6842.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6842.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6842.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6842.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6842.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6842.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6842.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6842.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6842.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6842.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6842.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6842.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6842.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6842.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6842.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6842.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6842.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6842.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6842.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6842.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6842.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6842.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6842.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6842.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6842.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6842.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6842.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6842.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6843.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6843.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6843.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6843.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6843.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6843.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6843.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6843.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6843.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6843.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6843.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6843.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6843.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6843.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6843.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6843.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6843.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6843.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6843.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6843.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6843.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6843.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6843.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6843.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6843.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6843.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6843.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6843.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6843.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6843.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6843.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6843.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6843.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6843.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6843.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6843.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6843.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6843.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6843.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6843.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6843.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6843.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6843.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6843.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6843.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6843.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6844.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6844.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6844.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6844.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6844.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6844.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6844.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6844.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6844.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6844.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6844.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6844.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6844.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6844.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6844.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6844.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6844.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6844.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6844.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6844.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6844.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6844.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6844.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6844.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6844.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6844.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6844.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6844.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6844.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6844.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6844.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6844.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6844.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6844.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6844.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6844.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6844.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6844.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6844.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6844.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6844.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6844.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6844.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6844.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6844.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6844.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6844.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6844.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6845.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6845.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6845.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6845.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6845.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6845.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6845.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6845.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6845.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6845.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6845.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6845.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6845.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6845.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6845.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6845.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6845.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6845.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6845.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6845.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6845.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6845.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6845.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6845.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6845.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6845.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6845.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6845.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6845.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6845.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6845.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6845.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6845.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6845.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6845.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6845.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6845.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6845.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6845.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6845.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6845.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6845.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6845.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6845.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6845.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6845.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6845.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6845.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6846.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6846.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6846.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6846.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6846.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6846.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6846.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6846.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6846.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6846.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6846.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6846.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6846.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6846.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6846.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6846.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6846.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6846.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6846.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6846.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6846.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6846.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6846.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6846.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6846.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6846.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6846.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6846.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6846.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6846.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6846.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6846.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6846.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6846.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6846.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6846.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6846.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6846.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6846.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6846.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6846.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6846.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6846.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6846.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6846.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6846.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6846.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6846.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6847.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6847.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6847.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6847.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6847.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6847.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6847.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6847.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6847.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6847.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6847.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6847.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6847.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6847.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6847.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6847.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6847.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6847.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6847.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6847.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6847.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6847.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6847.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6847.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6847.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6847.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6847.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6847.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6847.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6847.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6847.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6847.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6847.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6847.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6847.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6847.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6847.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6847.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6847.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6847.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6847.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6847.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6847.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6847.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6847.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6847.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6847.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6847.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6848.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6848.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6848.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6848.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6848.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6848.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6848.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6848.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6848.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6848.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6848.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6848.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6848.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6848.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6848.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6848.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6848.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6848.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6848.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6848.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6848.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6848.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6848.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6848.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6848.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6848.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6848.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6848.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6848.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6848.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6848.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6848.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6848.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6848.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6848.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6848.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6848.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6848.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6848.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6848.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6848.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6848.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6848.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6848.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6848.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6848.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6848.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6848.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6849.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6849.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6849.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6849.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6849.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6849.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6849.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6849.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6849.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6849.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6849.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6849.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6849.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6849.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6849.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6849.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6849.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6849.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6849.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6849.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6849.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6849.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6849.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6849.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6849.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6849.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6849.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6849.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6849.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6849.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6849.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6849.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6849.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6849.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6849.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6849.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6849.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6849.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6849.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6849.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6849.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6849.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6849.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6849.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6849.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6849.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6849.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6850.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6850.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6850.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6850.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6850.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6850.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6850.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6850.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6850.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6850.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6850.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6850.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6850.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6850.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6850.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6850.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6850.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6850.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6850.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6850.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6850.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6850.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6850.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6850.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6850.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6850.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6850.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6850.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6850.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6850.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6850.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6850.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6850.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6850.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6850.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6850.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6850.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6850.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6850.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6850.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6850.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6850.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6850.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6850.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6850.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6850.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6850.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6851.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6851.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6851.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6851.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6851.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6851.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6851.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6851.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6851.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6851.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6851.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6851.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6851.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6851.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6851.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6851.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6851.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6851.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6851.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6851.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6851.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6851.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6851.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6851.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6851.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6851.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6851.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6851.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6851.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6851.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6851.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6851.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6851.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6851.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6851.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6851.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6851.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6851.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6851.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6851.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6851.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6851.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6851.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6851.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6851.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6851.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6851.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6851.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6852.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6852.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6852.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6852.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6852.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6852.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6852.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6852.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6852.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6852.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6852.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6852.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6852.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6853.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6853.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6853.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6853.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6853.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6853.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6853.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6853.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6853.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6853.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6853.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6853.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6853.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6853.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6853.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6853.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6853.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6853.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6853.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6853.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6853.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6853.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6853.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6853.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6853.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6853.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6853.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6853.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6853.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6853.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6853.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6853.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6853.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6853.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6853.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6853.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6853.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6853.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6853.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6853.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6853.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6853.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6853.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6853.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6853.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6853.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6854.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6854.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6854.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6854.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6854.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6854.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6854.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6854.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6854.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6854.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6854.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6854.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6854.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6854.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6854.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6854.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6854.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6854.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6854.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6854.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6854.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6854.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6854.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6854.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6854.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6854.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6854.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6854.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6854.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6854.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6854.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6854.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6854.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6854.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6854.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6854.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6854.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6854.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6854.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6854.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6854.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6854.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6854.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6854.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6854.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6854.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6854.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6854.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6854.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6855.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6855.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6855.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6855.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6855.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6855.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6855.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6855.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6855.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6855.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6855.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6855.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6855.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6855.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6855.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6855.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6855.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6855.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6855.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6855.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6855.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6855.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6855.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6855.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6855.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6855.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6855.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6855.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6855.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6855.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6855.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6855.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6855.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6855.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6855.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6855.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6855.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6855.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6855.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6855.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6855.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6855.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6855.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6855.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6855.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6855.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6855.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6855.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6856.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6856.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6856.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6856.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6856.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6856.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6856.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6856.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6856.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6856.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6856.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6856.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6856.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6856.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6856.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6856.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6856.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6856.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6856.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6856.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6856.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6856.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6856.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6856.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6856.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6856.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6856.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6856.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6856.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6856.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6856.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6856.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6856.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6856.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6856.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6856.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6856.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6856.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6856.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6856.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6856.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6856.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6856.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6856.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6856.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6856.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6856.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6856.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6857.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6857.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6857.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6857.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6857.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6857.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6857.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6857.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6857.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6857.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6857.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6857.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6857.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6857.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6857.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6857.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6857.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6857.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6857.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6857.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6857.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6857.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6857.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6857.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6857.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6857.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6857.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6857.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6857.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6857.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6857.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6857.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6857.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6857.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6857.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6857.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6857.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6857.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6857.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6857.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6857.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6857.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6857.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6857.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6857.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6857.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6857.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6857.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6857.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6858.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6858.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6858.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6858.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6858.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6858.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6858.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6858.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6858.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6858.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6858.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6858.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6858.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6858.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6858.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6858.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6858.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6858.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6858.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6858.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6858.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6858.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6858.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6858.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6858.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6858.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6858.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6858.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6858.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6858.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6858.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6858.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6858.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6858.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6858.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6858.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6858.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6858.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6858.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6858.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6858.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6858.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6858.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6858.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6858.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6858.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6858.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6858.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6859.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6859.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6859.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6859.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6859.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6859.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6859.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6859.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6859.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6859.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6859.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6859.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6859.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6859.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6859.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6859.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6859.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6859.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6859.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6859.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6859.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6859.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6859.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6859.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6859.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6859.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6859.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6859.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6859.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6859.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6859.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6859.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6859.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6859.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6859.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6859.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6859.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6859.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6859.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6859.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6859.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6859.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6859.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6859.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6859.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6859.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6859.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6859.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6860.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6860.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6860.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6860.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6861.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6861.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6861.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6861.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6861.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6861.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6861.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6861.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6861.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6861.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6861.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6861.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6861.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6861.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6861.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6861.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6861.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6861.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6861.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6861.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6861.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6861.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6861.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6861.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6861.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6861.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6861.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6861.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6861.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6861.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6861.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6861.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6861.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6861.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6861.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6861.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6861.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6861.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6861.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6861.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6861.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6861.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6861.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6861.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6861.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6861.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6861.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6861.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6861.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6861.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6862.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6862.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6862.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6862.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6862.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6862.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6862.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6862.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6862.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6862.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6862.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6862.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6862.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6862.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6862.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6862.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6862.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6862.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6862.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6862.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6862.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6862.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6862.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6862.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6862.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6862.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6862.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6862.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6862.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6862.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6862.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6862.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6862.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6862.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6862.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6862.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6862.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6862.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6862.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6862.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6862.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6862.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6862.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6862.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6862.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6862.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6862.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6862.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6863.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6863.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6863.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6863.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6863.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6863.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6863.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6863.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6863.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6863.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6863.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6863.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6863.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6863.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6863.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6863.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6863.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6863.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6863.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6863.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6863.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6863.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6863.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6863.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6863.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6863.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6863.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6863.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6863.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6863.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6863.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6863.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6863.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6863.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6863.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6863.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6863.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6863.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6863.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6863.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6863.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6863.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6863.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6863.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6863.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6863.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6864.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6864.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6864.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6864.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6864.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6864.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6864.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6864.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6864.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6864.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6864.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6864.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6864.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6864.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6864.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6864.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6864.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6864.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6864.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6864.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6864.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6864.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6864.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6864.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6864.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6864.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6864.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6864.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6864.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6864.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6864.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6864.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6864.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6864.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6864.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6864.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6864.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6864.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6864.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6864.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6864.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6864.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6864.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6864.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6864.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6864.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6864.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6864.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6865.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6865.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6865.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6865.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6866.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6866.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6866.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6866.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6866.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6866.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6866.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6866.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6866.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6866.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6866.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6866.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6866.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6866.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6866.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6866.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6866.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6866.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6866.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6866.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6866.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6866.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6866.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6866.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6866.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6866.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6866.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6866.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6866.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6866.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6866.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6866.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6866.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6866.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6866.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6866.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6866.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6866.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6866.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6866.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6866.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6866.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6866.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6866.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6866.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6866.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6866.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6866.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6867.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6867.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6867.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6867.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6867.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6867.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6867.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6867.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6867.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6867.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6867.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6867.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6867.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6867.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6867.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6867.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6867.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6867.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6867.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6867.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6867.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6867.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6867.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6867.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6867.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6867.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6867.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6867.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6867.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6867.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6867.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6867.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6867.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6867.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6867.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6867.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6867.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6867.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6867.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6867.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6867.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6867.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6867.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6867.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6867.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6867.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6867.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6867.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6868.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6868.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6868.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6868.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6868.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6868.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6868.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6868.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6868.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6868.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6868.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6868.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6868.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6868.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6868.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6868.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6868.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6868.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6868.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6868.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6868.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6868.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6868.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6868.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6868.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6868.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6868.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6868.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6868.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6868.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6868.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6868.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6868.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6868.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6868.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6868.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6868.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6868.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6868.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6868.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6868.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6868.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6868.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6868.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6868.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6868.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6868.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6868.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6869.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6869.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6869.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6869.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6869.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6869.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6869.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6869.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6869.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6869.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6869.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6869.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6869.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6869.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6869.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6869.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6869.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6869.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6869.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6869.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6869.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6869.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6869.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6869.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6869.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6869.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6869.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6869.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6869.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6869.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6869.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6869.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6869.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6869.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6869.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6869.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6869.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6869.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6869.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6869.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6869.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6869.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6869.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6869.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6869.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6869.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6869.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6869.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6870.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6870.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6870.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6870.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6870.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6870.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6870.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6870.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6870.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6870.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6870.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6870.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6870.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6870.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6870.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6870.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6870.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6870.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6870.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6870.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6870.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6870.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6870.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6870.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6870.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6870.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6870.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6870.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6870.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6870.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6870.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6870.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6870.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6870.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6870.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6870.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6870.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6870.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6870.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6870.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6870.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6870.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6870.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6870.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6870.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6870.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6870.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6871.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6871.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6871.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6871.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6871.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6871.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6871.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6871.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6871.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6871.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6871.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6871.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6871.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6871.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6871.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6871.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6871.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6871.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6871.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6871.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6871.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6871.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6871.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6871.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6871.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6871.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6871.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6871.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6872.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6872.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6872.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6872.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6872.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6872.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6872.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6872.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6872.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6872.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6872.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6872.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6872.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6872.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6872.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6872.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6872.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6872.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6872.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6872.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6872.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6872.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6872.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6872.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6872.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6872.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6872.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6872.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6872.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6872.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6872.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6872.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6872.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6872.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6872.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6872.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6872.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6872.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6872.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6872.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6872.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6872.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6872.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6872.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6872.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6872.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6872.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6872.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6873.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6873.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6873.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6873.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6873.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6873.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6873.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6873.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6873.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6873.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6873.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6873.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6873.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6873.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6873.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6873.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6873.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6873.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6873.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6873.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6873.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6873.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6873.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6873.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6873.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6873.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6873.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6873.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6873.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6873.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6873.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6873.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6873.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6873.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6873.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6873.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6873.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6873.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6873.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6873.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6873.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6873.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6873.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6873.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6873.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6873.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6873.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6873.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6874.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6874.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6874.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6874.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6874.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6874.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6874.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6874.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6874.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6874.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6874.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6874.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6874.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6874.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6874.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6874.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6874.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6874.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6874.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6874.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6874.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6874.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6874.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6874.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6874.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6874.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6874.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6874.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6874.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6874.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6874.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6874.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6874.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6874.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6874.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6874.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6874.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6874.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6874.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6874.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6874.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6874.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6874.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6874.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6874.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6874.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6874.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6874.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6875.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6875.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6875.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6875.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6875.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6875.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6875.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6875.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6875.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6875.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6875.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6875.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6875.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6875.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6875.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6875.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6875.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6875.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6875.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6875.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6875.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6875.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6875.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6875.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6875.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6875.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6875.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6875.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6875.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6875.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6875.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6875.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6875.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6875.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6875.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6875.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6875.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6875.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6875.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6875.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6875.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6875.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6875.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6875.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6875.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6875.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6875.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6875.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6876.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6876.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6876.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6876.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6876.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6876.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6876.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6876.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6876.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6876.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6876.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6876.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6876.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6876.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6876.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6876.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6876.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6876.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6876.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6876.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6876.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6876.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6876.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6876.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6876.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6876.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6876.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6876.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6876.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6876.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6876.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6876.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6876.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6876.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6876.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6876.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6876.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6876.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6876.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6876.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6876.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6876.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6876.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6876.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6876.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6876.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6876.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6876.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6877.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6877.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6877.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6877.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6877.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6877.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6877.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6877.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6877.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6877.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6877.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6877.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6877.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6877.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6877.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6877.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6877.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6877.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6877.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6877.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6877.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6877.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6877.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6877.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6877.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6877.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6877.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6877.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6877.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6877.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6877.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6877.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6877.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6877.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6877.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6877.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6877.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6877.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6877.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6877.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6877.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6877.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6877.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6877.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6877.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6877.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6878.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6878.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6878.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6878.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6878.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6878.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6878.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6878.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6878.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6878.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6878.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6878.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6878.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6878.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6878.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6878.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6878.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6878.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6878.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6878.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6878.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6878.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6878.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6878.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6878.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6878.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6878.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6878.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6878.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6878.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6878.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6878.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6878.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6878.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6878.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6878.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6878.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6878.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6878.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6878.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6878.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6878.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6878.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6878.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6878.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6878.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6878.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6878.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6879.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6879.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6879.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6879.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6879.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6879.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6879.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6879.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6879.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6879.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6879.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6879.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6879.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6879.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6879.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6879.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6879.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6879.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6879.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6879.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6879.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6879.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6879.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6879.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6879.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6879.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6879.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6879.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6879.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6879.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6879.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6879.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6879.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6879.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6879.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6879.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6879.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6879.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6879.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6879.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6879.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6879.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6879.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6879.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6879.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6879.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6880.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6880.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6880.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6880.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6880.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6880.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6880.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6880.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6880.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6880.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6880.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6880.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6880.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6880.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6880.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6880.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6880.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6880.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6880.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6880.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6880.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6880.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6880.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6880.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6880.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6880.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6880.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6880.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6880.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6880.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6880.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6880.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6881.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6881.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6881.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6881.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6881.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6881.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6881.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6881.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6881.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6881.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6881.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6881.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6881.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6881.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6881.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6881.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6881.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6881.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6881.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6881.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6881.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6881.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6881.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6881.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6881.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6881.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6881.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6881.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6881.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6881.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6881.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6881.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6881.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6881.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6881.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6881.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6881.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6881.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6881.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6881.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6881.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6881.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6881.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6881.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6881.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6881.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6881.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6881.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6881.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6882.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6882.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6882.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6882.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6882.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6882.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6882.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6882.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6882.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6882.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6882.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6882.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6882.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6882.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6882.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6882.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6882.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6882.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6882.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6882.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6882.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6882.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6882.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6882.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6882.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6882.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6882.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6882.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6882.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6882.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6882.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6882.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6882.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6882.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6882.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6882.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6882.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6882.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6882.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6882.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6882.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6882.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6882.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6882.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6882.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6882.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6882.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6882.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6883.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6883.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6883.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6883.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6884.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6884.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6884.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6884.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6884.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6884.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6884.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6884.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6884.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6884.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6884.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6884.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6884.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6884.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6884.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6884.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6884.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6884.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6884.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6884.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6884.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6884.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6884.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6884.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6884.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6884.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6884.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6884.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6884.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6884.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6884.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6884.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6884.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6884.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6884.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6884.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6884.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6884.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6884.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6884.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6884.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6884.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6884.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6884.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6884.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6884.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6884.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6884.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6885.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6885.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6885.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6885.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6885.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6885.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6885.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6885.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6885.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6885.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6885.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6885.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6885.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6885.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6885.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6885.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6885.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6885.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6885.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6885.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6885.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6885.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6885.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6885.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6885.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6885.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6885.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6885.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6885.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6885.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6885.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6885.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6885.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6885.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6885.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6885.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6885.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6885.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6885.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6885.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6885.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6885.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6885.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6885.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6885.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6885.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6885.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6885.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6886.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6886.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6886.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6886.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6886.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6886.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6886.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6886.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6886.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6886.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6886.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6886.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6886.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6886.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6886.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6886.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6886.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6886.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6886.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6886.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6886.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6886.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6886.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6886.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6886.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6886.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6886.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6886.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6886.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6886.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6886.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6886.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6886.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6886.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6886.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6886.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6886.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6886.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6886.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6886.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6886.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6886.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6886.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6886.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6886.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6886.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6886.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6886.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6887.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6887.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6887.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6887.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6887.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6887.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6887.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6887.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6887.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6887.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6887.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6887.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6887.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6887.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6887.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6887.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6887.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6887.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6887.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6887.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6887.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6887.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6887.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6887.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6887.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6887.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6887.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6887.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6887.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6887.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6887.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6887.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6887.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6887.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6887.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6887.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6887.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6887.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6887.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6887.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6887.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6887.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6887.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6887.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6887.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6887.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6887.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6887.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6888.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6888.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6888.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6888.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6888.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6888.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6888.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6888.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6888.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6888.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6888.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6888.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6888.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6888.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6888.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6888.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6888.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6888.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6888.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6888.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6888.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6888.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6888.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6888.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6888.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6888.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6888.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6888.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6888.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6888.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6888.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6888.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6888.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6888.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6888.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6888.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6888.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6888.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6888.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6888.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6888.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6888.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6888.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6888.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6888.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6888.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6888.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6889.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6889.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6889.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6889.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6889.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6889.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6889.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6889.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6889.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6889.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6889.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6889.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6889.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6889.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6889.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6889.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6889.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6889.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6889.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6889.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6889.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6889.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6889.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6889.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6889.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6889.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6889.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6889.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6889.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6889.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6889.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6889.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6889.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6889.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6889.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6889.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6889.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6889.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6889.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6889.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6889.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6889.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6889.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6889.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6889.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6889.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6889.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6889.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6890.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6890.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6890.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6890.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6890.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6890.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6890.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6890.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6890.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6890.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6890.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6890.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6890.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6890.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6890.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6890.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6890.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6890.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6890.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6890.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6890.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6890.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6890.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6890.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6890.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6890.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6890.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6890.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6890.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6890.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6890.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6890.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6890.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6890.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6890.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6890.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6890.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6890.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6890.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6890.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6890.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6890.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6890.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6890.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6890.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6890.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6890.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6891.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6891.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6891.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6891.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6891.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6891.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6891.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6891.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6891.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6891.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6891.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6891.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6891.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6891.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6891.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6891.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6891.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6891.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6891.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6891.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6891.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6891.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6891.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6891.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6891.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6891.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6891.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6891.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6891.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6891.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6891.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6891.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6891.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6891.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6891.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6891.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6891.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6891.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6891.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6891.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6891.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6891.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6891.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6891.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6891.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6891.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6891.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6891.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6892.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6892.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6892.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6892.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6892.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6892.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6892.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6892.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6892.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6892.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6892.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6892.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6892.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6892.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6892.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6892.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6892.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6892.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6892.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6892.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6892.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6892.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6892.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6892.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6892.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6892.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6892.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6892.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6892.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6892.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6892.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6892.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6892.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6892.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6892.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6892.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6892.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6892.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6892.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6892.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6892.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6892.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6892.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6892.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6892.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6892.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6892.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6892.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6893.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6893.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6893.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6893.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6893.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6893.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6893.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6893.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6893.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6893.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6893.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6893.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6893.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6893.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6893.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6893.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6893.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6893.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6893.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6893.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6893.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6893.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6893.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6893.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6893.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6893.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6893.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6893.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6893.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6893.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6893.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6893.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6893.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6893.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6893.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6893.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6893.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6893.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6893.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6893.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6893.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6893.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6893.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6893.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6893.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6893.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6893.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6893.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6893.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6893.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6894.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6894.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6894.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6894.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6894.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6894.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6894.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6894.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6894.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6894.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6894.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6894.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6894.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6894.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6894.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6894.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6894.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6894.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6894.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6894.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6894.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6894.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6894.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6894.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6894.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6894.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6894.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6894.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6894.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6894.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6894.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6894.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6894.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6894.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6894.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6894.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6894.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6894.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6894.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6894.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6894.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6894.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6894.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6894.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6894.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6894.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6894.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6894.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6895.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6895.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6895.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6895.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6895.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6895.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6895.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6895.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6895.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6895.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6895.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6895.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6895.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6895.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6895.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6895.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6895.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6895.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6895.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6895.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6895.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6895.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6895.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6895.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6895.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6895.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6895.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6895.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6895.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6895.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6895.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6895.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6895.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6895.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6895.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6895.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6895.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6895.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6895.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6895.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6895.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6895.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6895.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6895.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6895.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6895.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6895.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6895.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6895.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6896.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6896.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6896.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6896.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6896.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6896.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6896.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6896.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6896.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6896.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6896.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6896.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6896.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6896.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6896.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6896.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6896.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6896.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6896.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6896.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6896.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6896.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6896.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6896.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6896.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6896.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6896.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6896.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6896.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6896.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6896.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6896.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6896.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6896.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6896.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6896.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6896.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6896.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6896.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6896.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6896.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6896.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6896.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6896.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6896.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6896.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6896.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6896.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6896.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6897.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6897.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6897.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6897.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6897.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6897.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6897.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6897.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6897.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6897.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6897.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6897.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6897.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6897.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6897.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6897.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6898.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6898.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6898.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6898.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6898.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6898.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6898.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6898.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6898.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6898.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6898.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6898.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6898.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6898.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6898.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6898.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6898.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6898.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6898.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6898.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6898.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6898.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6898.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6898.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6898.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6898.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6898.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6898.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6898.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6898.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6898.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6898.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6898.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6898.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6898.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6898.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6898.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6898.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6898.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6898.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6898.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6898.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6898.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6898.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6898.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6898.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6899.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6899.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6899.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6899.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6899.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6899.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6899.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6899.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6899.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6899.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6899.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6900.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6900.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6900.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6900.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6900.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6900.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6900.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6900.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6900.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6900.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6900.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6900.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6900.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6900.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6900.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6900.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6900.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6900.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6900.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6900.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6900.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6900.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6900.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6900.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6900.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6900.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6900.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6900.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6900.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6900.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6900.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6900.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6900.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6900.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6900.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6900.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6900.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6900.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6900.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6900.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6900.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6900.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6900.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6900.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6900.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6900.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6900.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6900.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6900.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6901.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6901.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6901.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6901.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6901.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6901.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6901.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6901.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6901.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6901.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6901.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6901.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6901.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6901.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6901.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6901.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6901.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6901.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6901.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6901.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6901.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6901.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6901.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6901.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6901.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6901.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6901.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6901.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6901.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6901.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6901.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6901.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6901.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6901.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6901.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6901.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6901.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6901.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6901.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6901.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6901.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6901.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6901.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6901.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6901.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6901.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6901.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6901.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6901.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6902.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6902.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6902.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6902.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6902.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6902.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6902.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6902.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6902.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6902.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6902.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6902.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6902.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6902.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6902.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6902.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6902.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6902.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6902.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6902.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6902.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6902.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6902.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6902.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6902.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6902.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6902.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6902.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6902.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6902.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6902.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6902.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6902.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6902.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6902.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6902.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6902.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6902.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6902.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6902.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6902.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6902.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6902.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6902.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6902.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6902.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6902.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6902.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6903.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6903.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6903.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6903.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6903.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6903.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6903.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6903.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6903.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6903.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6903.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6903.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6903.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6903.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6903.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6903.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6903.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6903.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6903.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6903.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6903.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6903.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6903.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6903.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6903.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6903.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6903.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6903.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6903.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6903.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6904.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6904.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6904.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6904.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6904.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6904.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6904.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6904.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6904.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6904.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6904.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6904.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6904.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6904.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6904.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6904.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6904.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6904.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6904.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6904.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6904.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6904.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6904.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6904.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6904.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6904.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6904.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6904.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6904.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6904.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6904.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6904.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6904.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6904.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6904.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6904.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6904.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6904.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6904.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6904.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6904.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6904.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6904.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6904.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6904.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6904.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6904.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6905.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6905.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6905.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6905.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6905.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6905.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6905.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6905.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6905.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6905.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6905.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6905.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6905.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6905.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6905.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6905.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6905.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6905.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6905.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6905.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6905.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6905.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6905.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6905.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6905.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6905.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6905.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6905.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6905.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6905.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6905.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6905.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6905.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6905.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6905.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6905.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6905.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6905.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6905.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6905.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6905.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6905.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6905.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6905.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6905.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6905.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6905.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6906.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6906.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6906.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6906.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6906.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6906.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6906.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6906.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6906.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6906.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6906.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6906.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6906.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6906.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6906.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6906.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6906.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6906.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6906.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6906.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6906.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6906.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6906.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6906.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6906.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6906.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6906.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6906.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6906.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6906.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6906.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6906.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6906.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6906.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6906.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6906.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6906.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6906.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6906.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6906.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6906.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6906.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6906.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6906.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6906.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6906.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6906.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6907.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6907.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6907.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6907.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6907.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6907.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6907.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6907.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6907.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6907.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6907.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6907.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6907.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6907.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6907.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6907.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6907.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6907.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6907.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6907.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6907.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6907.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6907.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6907.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6907.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6907.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6907.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6907.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6907.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6907.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6907.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6907.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6907.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6907.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6907.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6907.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6907.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6907.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6907.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6907.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6907.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6907.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6907.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6907.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6907.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6907.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6907.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6907.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6908.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6908.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6908.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6908.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6908.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6908.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6908.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6908.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6908.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6908.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6908.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6908.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6908.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6908.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6908.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6908.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6908.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6908.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6908.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6908.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6908.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6908.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6908.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6908.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6908.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6908.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6908.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6908.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6908.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6908.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6908.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6908.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6908.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6908.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6908.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6908.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6908.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6908.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6908.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6908.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6908.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6908.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6908.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6908.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6908.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6908.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6908.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6908.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6909.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6909.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6909.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6909.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6909.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6909.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6909.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6909.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6909.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6909.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6909.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6909.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6909.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6909.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6909.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6909.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6909.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6909.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6909.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6909.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6909.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6909.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6909.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6909.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6909.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6909.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6909.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6909.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6909.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6909.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6909.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6909.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6909.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6909.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6909.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6909.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6909.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6909.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6909.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6909.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6909.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6909.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6909.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6909.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6909.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6909.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6909.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6909.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6910.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6910.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6910.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6910.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6910.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6910.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6910.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6910.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6910.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6910.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6910.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6910.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6910.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6910.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6910.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6910.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6910.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6910.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6910.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6910.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6910.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6910.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6910.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6910.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6910.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6910.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6910.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6910.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6910.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6910.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6910.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6910.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6910.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6910.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6910.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6910.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6910.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6910.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6910.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6910.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6910.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6910.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6910.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6910.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6910.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6910.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6910.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6910.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6911.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6911.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6911.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6911.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6911.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6911.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6911.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6911.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6911.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6911.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6911.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6911.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6911.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6911.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6911.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6911.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6911.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6911.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6911.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6911.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6911.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6911.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6911.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6911.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6911.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6911.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6911.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6911.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6911.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6911.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6912.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6912.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6912.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6912.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6912.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6912.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6912.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6912.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6912.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6912.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6912.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6912.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6912.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6912.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6912.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6912.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6912.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6912.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6912.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6912.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6912.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6912.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6912.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6912.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6912.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6912.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6912.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6912.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6912.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6912.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6912.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6912.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6912.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6912.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6912.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6912.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6912.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6912.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6912.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6912.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6912.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6912.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6912.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6912.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6912.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6912.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6912.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6912.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6913.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6913.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6913.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6913.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6913.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6913.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6913.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6913.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6913.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6913.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6913.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6913.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6913.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6913.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6913.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6913.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6913.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6913.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6913.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6913.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6913.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6913.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6913.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6913.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6913.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6913.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6913.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6913.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6913.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6913.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6913.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6913.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6913.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6913.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6913.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6913.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6913.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6913.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6913.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6913.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6913.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6913.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6913.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6913.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6913.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6913.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6914.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6914.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6914.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6914.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6914.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6914.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6914.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6914.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6914.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6914.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6914.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6914.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6914.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6914.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6914.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6914.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6914.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6914.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6914.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6914.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6914.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6914.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6914.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6914.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6914.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6914.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6914.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6914.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6914.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6914.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6914.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6914.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6914.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6914.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6914.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6914.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6914.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6914.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6914.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6914.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6914.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6914.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6914.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6914.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6914.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6914.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6914.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6914.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6915.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6915.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6915.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6915.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6915.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6915.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6915.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6915.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6915.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6915.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6915.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6915.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6915.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6915.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6915.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6915.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6915.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6915.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6915.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6915.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6915.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6915.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6915.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6915.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6915.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6915.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6915.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6915.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6915.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6915.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6915.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6915.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6915.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6915.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6915.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6915.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6915.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6915.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6915.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6915.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6915.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6915.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6915.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6915.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6915.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6915.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6915.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6915.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6915.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6916.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6916.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6916.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6916.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6916.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6916.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6916.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6916.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6916.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6916.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6916.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6916.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6916.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6916.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6916.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6916.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6916.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6916.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6916.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6916.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6916.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6916.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6916.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6916.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6916.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6916.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6916.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6916.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6916.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6916.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6916.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6916.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6916.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6916.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6916.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6916.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6916.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6916.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6916.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6916.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6916.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6916.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6916.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6916.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6916.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6916.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6916.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6917.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6917.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6917.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6917.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6917.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6917.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6917.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6917.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6917.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6917.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6917.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6917.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6917.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6917.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6917.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6917.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6917.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6917.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6917.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6917.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6917.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6917.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6917.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6917.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6917.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6917.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6917.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6917.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6917.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6917.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6917.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6917.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6917.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6917.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6917.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6917.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6917.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6917.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6917.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6917.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6917.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6917.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6917.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6917.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6917.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6917.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6918.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6918.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6918.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6918.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6918.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6918.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6918.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6918.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6918.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6918.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6918.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6918.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6918.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6918.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6918.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6918.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6918.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6918.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6918.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6918.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6918.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6918.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6918.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6918.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6918.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6918.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6918.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6918.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6918.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6918.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6918.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6918.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6918.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6918.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6918.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6918.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6918.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6918.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6918.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6918.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6918.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6918.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6918.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6918.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6918.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6918.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6918.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6918.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6919.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6919.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6919.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6919.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6919.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6919.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6919.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6919.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6919.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6919.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6919.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6919.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6919.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6919.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6919.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6919.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6919.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6919.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6919.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6919.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6919.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6919.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6919.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6919.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6919.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6919.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6919.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6919.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6919.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6919.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6919.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6919.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6919.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6919.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6919.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6919.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6919.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6919.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6919.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6919.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6919.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6919.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6919.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6919.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6919.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6919.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6920.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6920.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6920.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6920.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6920.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6920.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6920.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6920.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6920.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6920.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6920.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6920.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6920.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6920.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6920.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6920.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6920.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6920.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6920.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6920.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6920.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6920.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6920.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6920.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6920.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6920.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6920.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6920.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6920.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6920.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6920.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6920.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6920.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6920.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6920.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6920.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6920.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6920.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6920.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6920.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6920.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6920.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6920.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6920.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6920.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6920.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6920.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6920.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6921.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6921.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6921.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6921.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6921.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6921.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6921.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6921.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6921.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6921.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6921.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6921.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6921.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6921.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6921.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6921.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6921.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6921.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6921.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6921.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6921.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6921.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6921.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6921.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6921.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6921.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6921.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6921.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6921.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6921.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6921.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6921.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6921.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6921.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6921.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6921.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6921.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6921.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6921.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6921.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6921.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6921.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6921.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6921.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6921.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6921.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6921.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6922.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6922.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6922.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6922.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6922.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6922.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6922.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6922.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6922.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6922.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6922.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6922.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6922.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6922.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6922.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6922.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6922.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6922.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6922.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6922.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6922.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6922.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6922.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6922.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6922.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6922.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6922.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6922.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6922.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6922.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6922.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6922.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6922.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6922.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6922.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6922.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6922.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6922.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6922.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6922.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6922.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6922.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6922.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6922.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6922.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6922.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6922.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6923.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6923.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6923.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6923.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6923.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6923.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6923.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6923.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6923.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6923.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6923.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6923.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6923.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6923.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6923.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6923.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6923.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6923.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6923.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6923.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6923.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6923.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6923.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6923.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6923.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6923.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6923.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6923.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6923.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6923.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6923.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6923.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6923.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6923.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6923.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6923.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6923.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6923.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6923.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6923.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6923.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6923.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6923.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6923.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6923.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6923.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6923.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6923.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6924.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6924.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6924.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6924.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6924.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6924.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6924.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6924.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6924.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6924.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6924.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6924.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6924.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6924.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6924.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6924.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6924.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6924.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6924.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6924.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6924.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6924.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6924.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6924.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6924.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6924.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6924.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6924.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6924.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6924.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6924.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6924.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6924.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6924.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6924.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6924.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6924.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6924.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6924.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6924.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6924.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6924.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6924.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6924.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6924.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6924.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6924.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6924.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6925.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6925.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6925.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6925.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6925.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6925.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6925.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6925.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6925.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6925.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6925.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6925.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6925.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6925.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6925.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6925.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6925.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6925.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6925.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6925.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6925.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6925.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6925.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6925.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6925.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6925.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6925.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6925.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6925.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6925.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6925.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6925.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6925.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6925.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6925.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6925.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6925.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6925.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6925.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6925.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6925.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6925.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6925.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6925.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6925.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6925.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6925.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6925.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6926.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6926.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6926.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6926.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6926.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6926.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6926.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6926.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6926.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6926.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6926.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6926.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6926.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6926.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6926.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6926.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6926.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6926.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6926.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6926.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6926.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6926.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6926.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6926.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6926.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6926.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6926.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6926.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6926.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6926.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6926.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6926.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6926.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6926.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6926.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6926.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6926.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6926.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6926.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6926.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6926.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6926.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6926.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6926.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6926.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6926.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6926.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6926.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6926.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6926.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6927.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6927.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6927.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6927.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6927.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6927.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6927.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6927.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6927.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6927.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6927.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6927.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6927.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6927.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6927.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6927.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6927.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6927.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6927.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6927.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6927.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6927.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6927.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6927.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6927.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6927.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6927.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6927.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6927.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6927.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6927.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6927.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6927.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6927.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6927.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6927.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6927.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6927.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6927.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6927.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6927.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6927.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6927.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6927.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6927.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6927.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6927.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6927.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6928.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6928.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6928.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6928.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6928.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6928.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6928.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6928.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6928.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6928.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6928.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6928.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6928.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6928.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6928.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6928.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6928.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6928.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6928.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6928.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6928.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6928.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6928.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6928.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6928.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6928.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6928.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6928.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6928.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6928.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6928.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6928.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6928.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6928.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6928.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6928.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6928.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6928.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6928.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6928.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6928.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6928.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6928.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6928.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6928.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6928.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6928.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6928.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6929.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6929.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6929.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6929.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6929.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6929.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6929.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6929.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6929.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6929.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6929.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6929.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6929.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6929.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6929.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6929.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6929.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6929.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6929.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6929.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6929.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6929.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6929.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6929.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6929.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6929.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6929.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6929.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6929.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6929.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6929.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6929.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6929.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6929.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6929.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6929.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6929.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6929.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6929.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6929.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6929.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6929.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6929.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6929.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6929.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6929.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6929.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6929.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6929.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6929.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6930.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6930.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6930.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6930.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6930.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6930.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6930.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6930.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6930.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6930.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6930.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6930.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6930.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6930.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6930.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6930.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6930.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6930.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6930.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6930.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6930.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6930.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6930.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6930.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6930.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6930.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6930.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6930.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6930.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6930.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6930.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6930.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6930.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6930.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6930.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6930.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6930.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6930.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6930.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6930.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6930.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6930.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6930.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6930.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6930.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6930.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6930.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6930.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6931.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6931.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6931.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6931.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6931.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6931.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6931.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6931.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6931.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6931.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6931.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6931.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6931.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6931.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6931.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6931.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6931.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6931.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6931.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6931.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6931.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6931.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6931.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6931.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6931.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6931.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6931.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6931.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6931.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6931.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6931.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6931.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6931.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6931.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6931.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6931.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6931.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6931.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6931.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6931.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6931.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6931.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6931.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6931.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6931.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6931.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6931.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6932.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6932.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6932.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6932.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6932.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6932.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6932.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6932.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6932.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6932.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6932.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6932.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6932.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6932.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6932.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6932.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6932.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6932.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6932.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6932.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6932.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6932.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6932.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6932.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6932.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6932.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6932.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6932.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6932.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6932.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6932.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6932.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6932.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6932.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6932.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6932.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6932.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6932.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6932.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6932.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6932.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6932.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6932.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6932.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6932.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6932.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6932.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6932.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6932.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6933.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6933.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6933.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6933.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6933.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6933.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6933.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6933.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6933.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6933.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6933.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6933.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6933.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6933.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6933.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6933.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6933.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6933.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6933.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6933.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6933.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6933.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6933.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6933.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6933.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6933.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6933.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6933.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6933.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6933.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6933.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6933.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6933.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6933.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6933.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6933.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6933.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6933.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6933.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6933.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6933.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6933.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6933.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6933.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6933.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6933.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6934.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6934.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6934.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6934.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6934.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6934.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6934.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6934.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6934.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6934.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6934.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6934.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6934.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6934.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6934.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6934.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6934.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6934.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6934.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6934.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6934.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6934.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6934.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6934.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6934.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6934.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6934.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6934.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6934.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6934.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6934.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6934.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6934.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6934.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6934.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6934.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6934.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6934.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6934.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6934.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6935.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6935.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6935.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6935.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6935.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6935.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6935.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6935.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6935.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6935.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6936.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6936.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6936.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6936.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6936.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6936.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6936.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6936.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6936.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6936.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6936.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6936.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6937.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6937.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6937.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6937.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6937.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6937.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6937.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6937.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6937.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6937.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6937.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6937.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6937.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6937.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6937.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6937.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6937.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6937.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6937.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6937.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6937.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6937.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6937.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6937.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6937.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6937.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6937.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6937.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6937.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6937.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6937.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6937.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6937.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6937.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6937.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6937.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6937.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6937.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6937.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6937.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6937.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6937.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6937.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6937.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6937.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6937.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6937.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6937.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6937.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6938.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6938.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6938.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6938.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6938.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6938.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6938.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6938.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6938.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6938.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6938.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6938.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6938.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6938.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6938.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6938.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6938.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6938.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6938.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6938.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6938.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6938.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6938.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6938.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6938.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6938.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6938.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6938.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6938.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6938.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6938.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6938.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6938.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6938.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6938.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6938.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6938.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6938.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6938.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6938.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6938.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6938.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6938.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6938.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6938.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6938.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6938.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6938.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6939.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6939.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6939.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6939.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6939.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6939.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6939.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6939.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6939.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6939.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6939.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6939.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6939.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6939.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6939.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6939.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6939.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6939.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6939.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6939.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6939.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6939.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6939.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6939.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6939.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6939.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6939.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6939.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6939.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6939.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6939.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6939.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6939.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6939.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6939.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6939.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6939.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6939.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6939.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6939.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6939.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6939.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6939.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6939.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6939.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6939.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6939.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6939.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6939.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6940.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6940.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6940.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6940.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6940.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6940.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6940.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6940.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6940.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6940.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6940.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6940.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6940.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6940.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6940.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6940.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6940.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6940.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6940.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6940.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6940.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6940.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6940.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6940.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6940.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6940.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6940.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6940.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6940.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6940.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6940.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6940.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6940.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6940.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6940.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6940.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6940.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6940.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6940.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6940.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6940.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6940.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6940.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6940.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6940.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6940.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6940.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6941.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6941.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6941.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6941.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6941.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6941.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6941.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6941.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6941.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6941.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6941.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6941.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6941.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6941.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6941.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6941.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6941.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6941.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6941.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6941.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6941.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6941.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6941.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6941.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6941.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6941.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6941.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6941.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6941.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6941.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6941.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6941.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6941.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6941.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6941.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6941.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6941.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6941.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6941.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6941.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6941.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6941.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6941.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6941.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6941.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6941.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6941.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6942.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6942.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6942.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6942.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6942.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6942.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6942.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6942.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6942.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6942.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6942.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6942.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6942.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6942.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6942.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6942.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6942.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6942.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6942.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6942.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6942.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6942.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6942.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6942.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6942.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6942.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6942.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6942.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6942.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6942.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6942.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6942.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6942.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6942.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6942.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6942.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6942.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6942.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6942.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6942.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6942.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6942.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6942.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6942.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6942.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6942.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6942.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6942.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6943.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6943.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6943.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6943.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6943.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6943.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6943.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6943.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6943.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6943.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6943.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6943.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6943.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6943.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6943.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6943.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6943.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6943.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6943.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6943.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6943.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6943.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6943.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6943.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6943.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6943.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6943.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6943.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6943.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6943.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6943.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6943.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6943.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6943.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6943.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6943.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6943.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6943.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6943.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6943.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6943.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6943.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6943.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6943.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6943.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6943.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6943.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6943.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6943.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6943.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6944.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6944.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6944.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6944.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6944.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6944.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6944.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6944.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6944.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6944.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6944.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6944.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6944.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6944.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6944.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6944.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6944.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6944.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6944.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6944.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6944.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6944.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6944.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6944.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6944.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6944.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6944.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6944.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6944.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6944.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6944.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6944.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6944.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6944.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6944.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6944.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6944.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6944.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6944.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6944.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6944.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6944.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6944.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6944.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6944.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6944.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6944.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6945.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6945.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6945.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6945.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6945.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6945.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6945.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6945.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6945.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6945.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6945.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6945.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6945.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6945.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6945.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6945.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6945.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6945.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6945.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6945.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6945.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6945.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6945.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6945.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6945.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6945.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6945.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6945.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6945.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6945.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6945.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6945.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6945.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6945.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6945.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6945.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6945.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6945.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6945.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6945.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6945.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6945.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6945.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6945.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6945.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6945.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6945.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6945.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6945.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6946.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6946.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6946.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6946.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6946.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6946.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6946.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6946.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6946.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6946.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6946.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6946.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6946.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6947.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6947.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6947.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6947.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6947.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6947.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6947.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6947.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6947.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6947.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6947.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6947.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6947.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6947.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6947.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6947.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6947.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6947.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6947.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6947.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6947.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6947.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6947.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6947.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6947.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6947.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6947.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6947.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6947.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6947.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6947.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6947.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6947.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6947.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6947.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6947.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6947.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6947.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6947.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6947.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6947.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6947.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6947.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6947.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6947.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6947.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6948.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6948.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6948.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6948.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6948.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6948.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6948.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6948.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6948.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6948.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6948.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6948.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6948.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6948.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6948.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6948.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6948.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6948.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6948.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6948.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6948.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6948.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6948.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6948.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6948.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6948.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6948.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6948.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6948.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6948.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6948.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6948.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6948.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6948.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6948.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6948.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6948.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6948.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6948.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6948.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6948.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6948.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6948.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6948.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6948.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6948.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6948.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6948.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6949.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6949.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6949.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6949.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6949.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6949.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6949.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6949.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6949.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6949.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6949.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6949.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6949.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6949.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6949.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6949.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6949.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6949.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6949.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6949.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6949.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6949.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6949.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6949.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6949.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6949.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6949.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6949.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6949.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6949.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6949.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6949.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6949.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6949.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6949.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6949.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6949.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6949.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6949.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6949.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6949.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6949.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6949.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6949.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6949.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6949.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6949.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6949.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6950.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6950.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6950.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6950.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6950.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6950.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6950.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6950.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6950.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6950.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6950.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6950.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6950.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6950.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6950.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6950.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6950.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6950.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6950.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6950.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6950.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6950.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6950.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6950.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6950.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6950.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6950.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6950.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6950.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6950.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6950.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6950.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6950.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6950.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6950.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6950.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6950.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6950.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6950.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6950.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6950.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6950.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6950.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6950.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6950.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6950.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6950.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6950.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6951.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6951.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6951.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6951.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6951.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6951.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6951.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6951.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6951.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6951.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6951.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6951.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6951.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6951.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6951.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6951.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6951.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6951.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6951.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6951.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6951.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6951.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6951.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6951.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6951.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6951.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6951.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6951.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6951.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6951.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6951.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6951.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6951.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6951.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6951.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6951.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6951.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6951.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6951.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6951.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6951.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6951.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6951.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6951.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6951.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6951.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6952.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6952.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6952.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6952.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6952.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6952.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6952.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6952.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6952.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6952.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6952.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6952.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6952.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6952.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6952.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6952.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6952.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6952.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6952.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6952.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6952.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6952.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6952.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6952.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6952.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6952.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6952.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6952.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6952.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6952.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6952.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6952.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6952.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6952.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6952.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6952.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6952.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6952.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6952.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6952.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6952.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6952.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6952.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6952.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6952.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6952.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6952.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6952.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6953.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6953.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6953.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6953.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6954.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6954.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6954.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6954.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6954.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6954.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6954.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6954.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6954.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6954.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6954.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6954.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6954.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6954.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6954.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6954.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6954.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6954.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6954.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6954.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6954.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6954.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6954.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6954.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6954.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6954.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6954.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6954.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6954.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6954.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6954.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6954.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6954.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6954.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6954.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6954.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6954.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6954.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6954.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6954.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6954.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6954.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6954.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6954.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6954.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6954.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6954.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6954.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6955.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6955.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6955.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6955.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6955.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6955.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6955.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6955.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6955.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6955.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6955.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6955.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6955.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6955.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6955.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6955.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6955.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6955.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6955.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6955.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6955.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6955.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6955.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6955.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6955.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6955.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6955.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6955.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6955.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6955.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6955.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6955.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6955.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6955.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6955.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6955.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6955.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6955.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6955.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6955.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6955.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6955.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6955.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6955.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6955.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6955.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6956.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6956.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6956.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6956.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6956.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6956.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6956.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6956.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6956.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6956.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6956.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6956.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6956.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6956.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6956.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6956.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6956.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6956.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6956.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6956.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6956.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6956.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6956.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6956.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6956.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6956.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6956.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6956.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6956.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6956.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6956.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6956.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6956.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6956.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6956.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6956.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6956.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6956.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6956.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6956.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6956.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6956.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6956.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6956.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6956.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6956.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6956.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6956.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6957.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6957.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6957.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6957.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6957.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6957.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6957.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6957.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6957.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6957.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6957.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6957.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6957.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6957.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6957.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6957.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6957.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6957.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6957.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6957.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6957.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6957.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6957.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6957.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6957.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6957.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6957.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6957.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6957.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6957.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6957.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6957.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6957.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6957.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6957.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6957.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6957.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6957.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6957.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6957.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6957.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6957.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6957.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6957.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6957.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6957.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6957.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6957.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6958.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6958.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6958.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6958.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6958.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6958.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6958.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6958.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6958.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6958.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6958.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6958.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6958.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6958.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6958.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6958.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6958.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6958.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6958.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6958.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6958.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6958.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6958.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6958.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6958.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6958.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6958.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6958.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6958.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6958.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6958.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6958.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6958.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6958.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6958.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6958.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6958.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6958.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6958.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6958.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6958.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6958.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6958.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6958.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6958.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6958.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6958.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6958.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6959.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6959.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6959.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6959.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6959.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6959.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6959.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6959.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6959.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6959.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6959.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6959.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6959.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6959.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6959.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6959.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6959.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6959.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6959.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6959.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6959.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6959.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6959.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6959.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6959.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6959.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6959.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6959.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6959.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6959.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6959.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6959.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6959.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6959.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6959.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6959.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6959.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6959.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6959.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6959.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6959.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6959.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6959.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6959.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6959.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6959.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6959.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6959.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6959.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6960.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6960.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6960.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6960.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6960.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6960.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6960.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6960.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6960.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6960.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6960.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6960.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6960.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6960.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6960.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6960.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6960.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6960.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6960.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6960.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6960.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6960.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6960.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6960.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6960.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6960.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6960.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6960.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6960.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6960.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6960.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6960.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6960.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6960.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6960.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6960.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6960.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6960.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6960.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6960.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6960.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6960.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6960.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6960.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6960.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6960.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6960.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6961.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6961.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6961.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6961.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6961.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6961.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6961.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6961.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6961.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6961.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6961.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6961.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6961.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6961.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6961.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6961.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6961.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6961.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6961.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6961.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6961.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6961.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6961.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6961.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6961.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6961.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6961.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6961.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6961.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6961.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6961.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6962.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6962.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6962.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6962.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6962.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6962.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6962.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6962.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6962.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6962.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6962.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6962.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6962.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6962.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6962.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6962.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6962.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6962.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6962.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6962.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6962.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6962.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6962.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6962.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6962.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6962.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6962.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6962.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6962.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6962.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6962.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6962.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6962.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6962.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6962.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6962.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6962.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6962.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6962.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6962.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6962.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6962.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6962.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6962.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6962.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6962.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6962.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6962.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6962.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6963.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6963.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6963.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6963.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6963.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6963.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6963.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6963.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6963.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6963.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6963.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6963.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6963.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6963.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6963.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6963.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6963.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6963.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6963.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6963.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6963.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6963.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6963.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6963.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6963.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6964.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6964.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6964.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6964.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6964.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6964.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6964.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6964.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6964.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6964.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6964.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6964.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6964.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6964.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6964.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6964.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6964.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6964.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6964.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6964.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6964.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6964.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6964.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6964.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6964.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6964.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6964.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6964.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6964.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6964.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6964.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6964.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6964.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6964.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6964.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6964.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6964.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6964.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6964.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6964.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6964.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6964.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6964.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6964.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6964.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6964.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6964.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6965.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6965.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6965.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6965.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6965.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6965.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6965.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6965.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6965.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6965.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6965.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6965.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6965.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6965.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6965.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6965.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6965.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6965.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6965.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6965.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6965.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6965.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6965.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6965.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6965.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6965.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6965.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6965.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6965.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6965.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6965.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6965.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6965.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6965.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6965.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6965.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6965.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6965.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6965.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6965.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6965.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6965.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6965.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6965.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6965.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6965.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6965.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6966.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6966.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6966.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6966.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6966.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6966.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6966.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6966.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6966.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6966.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6966.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6966.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6966.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6966.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6966.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6966.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6966.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6966.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6966.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6966.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6966.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6966.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6966.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6966.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6966.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6966.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6966.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6966.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6966.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6966.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6966.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6966.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6966.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6966.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6966.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6966.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6966.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6966.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6966.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6966.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6966.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6966.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6966.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6966.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6966.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6966.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6966.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6966.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6967.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6967.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6967.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6967.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6967.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6967.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6967.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6967.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6967.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6968.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6968.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6968.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6968.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6968.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6968.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6968.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6968.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6968.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6968.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6968.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6968.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6968.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6968.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6968.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6968.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6968.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6968.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6968.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6968.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6968.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6968.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6968.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6968.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6968.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6968.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6968.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6968.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6968.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6968.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6968.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6968.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6968.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6968.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6968.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6968.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6968.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6968.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6968.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6968.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6968.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6968.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6968.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6968.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6968.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6968.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6968.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6968.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6968.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6969.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6969.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6969.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6969.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6969.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6969.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6969.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6969.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6969.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6969.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6969.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6969.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6969.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6969.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6969.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6969.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6969.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6969.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6969.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6969.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6969.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6969.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6969.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6969.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6969.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6969.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6969.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6969.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6969.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6969.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6969.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6969.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6969.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6969.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6969.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6969.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6969.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6969.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6969.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6969.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6969.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6969.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6969.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6969.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6969.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6969.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6969.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6969.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6970.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6970.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6970.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6970.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6970.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6970.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6970.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6970.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6970.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6970.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6970.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6970.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6970.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6970.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6970.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6970.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6970.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6970.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6970.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6970.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6970.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6970.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6970.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6970.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6970.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6970.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6970.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6970.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6970.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6970.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6970.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6970.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6970.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6970.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6970.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6970.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6970.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6970.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6970.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6970.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6970.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6970.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6970.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6970.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6970.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6970.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6970.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6970.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6971.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6971.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6971.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6971.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6971.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6971.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6971.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6971.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6971.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6971.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6971.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6971.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6971.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6971.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6971.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6971.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6971.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6971.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6971.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6971.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6971.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6971.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6971.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6971.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6971.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6971.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6971.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6971.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6971.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6971.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6971.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6971.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6971.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6971.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6971.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6971.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6971.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6971.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6971.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6971.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6971.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6971.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6971.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6971.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6971.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6971.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6971.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6971.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6972.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6972.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6972.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6972.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6972.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6972.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6972.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6972.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6972.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6972.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6972.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6972.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6972.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6972.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6972.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6972.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6972.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6972.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6972.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6972.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6972.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6972.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6972.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6972.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6972.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6972.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6972.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6972.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6972.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6972.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6972.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6972.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6972.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6972.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6972.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6972.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6972.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6972.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6972.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6972.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6972.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6972.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6972.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6972.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6972.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6972.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6972.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6972.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6973.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6973.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6973.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6973.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6973.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6973.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6973.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6973.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6973.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6973.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6973.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6973.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6973.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6973.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6973.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6973.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6973.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6973.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6973.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6973.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6973.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6973.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6973.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6973.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6973.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6973.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6973.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6973.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6973.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6974.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6974.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6974.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6974.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6974.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6974.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6974.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6975.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6975.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6975.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6975.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6975.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6975.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6975.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6975.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6975.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6975.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6975.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6975.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6975.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6976.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6976.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6976.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6976.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6976.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6976.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6976.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6976.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6976.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6976.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6976.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6976.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6976.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6976.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6976.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6976.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6976.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6976.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6976.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6976.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6976.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6976.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6976.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6976.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6976.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6976.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6976.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6976.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6976.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6976.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6976.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6976.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6976.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6976.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6976.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6976.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6976.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6976.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6976.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6976.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6976.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6976.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6976.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6976.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6976.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6976.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6976.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6976.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6977.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6977.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6977.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6977.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6977.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6977.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6977.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6977.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6977.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6977.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6977.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6977.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6977.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6977.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6977.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6977.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6977.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6977.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6977.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6977.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6977.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6977.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6977.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6977.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6977.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6977.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6977.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6977.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6977.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6977.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6977.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6977.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6977.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6977.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6977.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6977.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6977.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6977.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6977.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6977.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6977.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6977.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6977.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6977.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6977.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6977.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6977.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6977.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6978.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6978.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6978.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6978.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6978.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6978.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6978.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6978.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6978.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6978.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6978.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6978.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6978.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6978.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6978.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6978.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6978.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6978.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6978.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6978.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6978.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6978.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6978.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6978.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6978.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6978.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6978.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6978.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6978.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6978.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6978.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6978.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6978.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6978.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6978.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6978.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6978.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6978.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6978.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6978.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6978.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6978.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6978.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6978.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6978.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6978.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6978.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6978.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6978.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6979.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6979.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6979.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6979.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6979.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6979.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6979.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6979.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6979.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6979.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6979.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6979.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6979.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6979.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6979.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6979.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6979.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6979.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6979.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6979.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6979.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6979.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6979.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6979.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6979.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6979.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6979.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6979.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6979.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6979.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6979.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6979.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6979.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6979.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6979.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6979.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6979.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6979.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6979.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6979.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6979.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6979.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6979.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6979.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6979.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6979.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6980.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6980.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6980.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6980.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6980.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6980.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6980.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6980.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6980.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6980.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6980.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6980.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6980.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6980.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6980.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6980.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6980.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6980.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6980.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6980.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6980.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6980.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6980.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6980.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6980.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6980.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6980.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6980.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6980.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6980.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6980.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6980.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6980.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6980.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6980.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6980.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6980.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6980.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6980.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6980.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6980.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6980.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6980.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6980.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6980.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6980.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6980.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6980.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6981.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6981.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6981.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6981.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6981.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6981.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6981.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6981.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6981.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6981.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6981.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6981.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6981.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6981.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6981.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6981.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6981.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6981.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6981.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6981.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6981.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6981.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6981.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6981.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6981.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6981.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6981.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6981.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6981.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6981.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6981.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6981.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6981.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6981.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6981.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6981.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6981.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6981.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6981.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6981.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6981.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6981.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6981.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6981.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6981.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6981.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6981.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6981.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6981.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6982.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6982.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6982.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6982.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6982.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6982.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6982.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6982.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6982.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6982.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6982.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6982.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6982.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6982.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6982.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6982.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6982.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6982.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6982.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6982.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6982.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6982.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6982.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6982.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6982.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6982.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6982.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6982.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6982.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6982.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6982.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6982.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6982.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6982.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6982.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6982.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6982.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6982.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6982.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6982.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6982.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6982.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6982.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6982.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6982.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6982.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6982.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6982.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6982.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6983.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6983.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6983.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6983.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6983.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6983.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6983.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6983.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6983.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6983.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6983.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6983.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6983.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6983.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6983.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6983.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6983.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6983.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6983.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6983.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6983.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6983.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6983.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6983.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6983.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6983.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6983.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6983.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6983.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6983.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6983.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6983.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6983.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6983.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6983.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6983.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6983.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6983.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6983.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6983.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6983.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6983.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6983.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6983.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6983.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6983.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6983.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6983.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6984.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6984.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6984.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6984.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6984.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6984.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6984.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6984.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6984.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6984.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6984.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6984.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6984.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6984.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6984.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6984.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6984.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6984.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6984.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6984.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6984.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6984.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6984.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6984.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6984.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6984.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6984.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6984.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6984.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6984.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6984.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6984.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6984.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6984.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6984.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6984.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6984.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6984.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6984.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6984.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6984.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6984.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6984.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6984.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6984.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6984.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6984.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6984.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6985.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6985.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6985.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6985.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6985.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6985.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6985.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6985.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6985.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6985.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6985.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6985.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6985.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6985.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6985.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6985.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6985.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6985.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6985.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6985.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6985.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6985.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6985.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6985.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6985.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6985.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6985.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6985.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6985.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6985.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6985.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6985.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6985.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6985.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6985.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6985.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6985.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6985.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6985.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6985.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6985.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6985.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6985.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6985.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6985.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6985.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6985.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6985.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6986.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6986.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6986.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6986.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6986.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6986.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6986.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6986.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6986.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6986.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6986.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6986.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6986.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6986.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6986.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6986.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6986.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6986.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6986.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6986.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6986.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6986.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6986.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6986.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6986.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6986.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6986.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6986.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6986.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6986.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6986.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6986.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6986.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6986.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6986.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6986.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6986.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6986.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6986.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6986.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6986.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6986.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6986.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6986.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6986.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6986.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6986.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6986.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6986.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6986.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6987.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6987.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6987.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6987.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6987.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6987.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6987.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6987.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6987.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6987.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6987.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6987.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6987.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6987.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6987.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6987.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6987.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6987.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6987.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6987.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6987.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6987.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6987.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6987.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6987.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6987.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6987.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6987.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6987.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6987.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6987.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6987.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6987.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6987.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6987.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6987.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6987.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6987.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6987.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6987.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6987.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6987.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6987.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6987.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6987.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6987.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6987.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6987.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6988.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6988.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6988.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6988.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6988.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6988.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6988.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6988.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6988.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6988.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6988.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6988.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6988.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6988.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6988.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6988.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6988.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6988.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6988.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6988.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6988.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6988.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6988.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6988.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6988.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6988.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6988.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6988.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6988.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6988.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6988.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6988.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6988.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6988.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6988.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6988.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6988.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6988.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6988.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6988.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6988.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6988.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6988.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6988.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6988.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6988.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6988.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6988.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6989.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6989.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6989.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6989.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6989.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6989.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6989.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6989.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6989.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6989.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6989.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6989.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6989.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6989.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6989.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6989.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6989.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6989.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6989.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6989.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6989.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6989.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6989.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6989.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6989.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6989.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6989.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6989.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6989.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6989.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6989.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6989.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6989.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6989.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6989.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6989.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6989.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6989.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6989.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6989.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6989.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6989.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6989.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6989.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6989.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6989.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6990.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6990.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6990.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6990.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6990.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6990.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6990.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6990.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6990.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6990.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6990.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6990.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6990.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6990.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6990.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6990.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6990.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6990.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6990.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6990.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6990.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6990.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6990.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6990.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6990.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6990.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6990.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6990.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6990.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6990.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6990.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6990.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6990.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6990.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6990.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6990.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6990.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6990.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6990.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6990.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6991.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6991.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6991.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6991.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6991.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6991.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6991.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6991.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6991.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6991.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6991.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6991.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6991.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6991.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6991.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6991.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6991.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6991.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6991.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6991.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6991.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6991.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6991.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6991.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6991.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6991.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6991.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6991.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6991.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6991.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6991.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6991.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6991.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6992.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6992.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6992.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6992.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6992.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6992.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6992.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6992.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6992.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6992.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6992.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6992.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6992.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6992.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6992.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6992.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6992.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6992.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6992.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6992.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6992.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6992.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6992.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6992.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6992.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6992.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6992.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6992.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6992.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6992.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6992.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6992.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6992.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6992.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6992.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6992.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6992.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6992.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6992.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6992.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6992.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6992.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6992.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6992.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6992.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6992.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6992.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6992.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6993.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6993.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6993.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6993.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6994.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6994.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6994.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6994.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6994.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6994.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6994.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6994.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6994.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6994.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6994.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6994.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6994.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6994.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6994.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6994.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6994.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6994.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6994.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6994.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6994.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6994.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6994.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6994.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6994.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6994.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6994.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6994.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6994.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6994.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6994.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6994.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6994.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6994.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6994.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6994.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6994.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6994.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6994.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6994.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6994.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6994.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6994.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6994.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6994.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6994.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6994.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6994.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6995.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6995.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6995.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6995.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6995.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6995.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6995.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6995.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6995.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6995.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6995.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6995.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6995.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6995.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6995.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6995.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6995.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6995.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6995.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6995.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6995.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6995.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6995.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6995.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6995.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6995.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6995.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6995.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6995.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6995.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6995.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6995.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6995.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6996.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6996.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6996.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6996.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6996.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6996.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6996.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6996.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6996.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6996.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6996.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6996.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6996.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6996.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6996.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6996.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6996.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6996.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6996.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6996.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6996.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6996.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6996.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6996.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6996.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6996.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6996.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6996.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6996.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6996.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6996.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6996.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6996.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6996.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6996.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6996.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6996.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6996.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6996.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6996.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6996.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6996.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6996.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6996.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6996.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6996.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6996.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6996.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6997.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6997.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6997.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6997.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6997.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6997.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6997.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6997.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6997.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6997.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6997.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6997.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6997.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6997.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6997.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6997.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6997.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6997.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6997.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6997.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6997.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6997.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6997.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6997.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6997.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6997.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6997.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6997.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6997.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6997.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6997.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6997.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6997.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6997.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6997.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6997.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6997.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6997.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6997.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6997.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6997.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6997.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6997.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6997.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6997.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6997.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6997.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6997.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6998.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6998.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6998.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6998.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6998.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6998.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6998.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6998.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6998.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6998.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6998.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6998.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6998.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6998.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6998.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6998.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6998.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6998.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6998.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6998.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6998.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6998.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6998.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6998.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6998.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6998.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6998.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6998.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6998.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6998.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6998.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6998.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6998.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6998.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6998.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6998.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6998.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6998.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6998.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6998.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6998.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6998.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6998.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6998.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6998.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6998.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6998.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6998.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6999.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6999.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6999.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 6999.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 6999.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6999.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6999.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 6999.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 6999.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6999.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6999.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6999.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6999.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 6999.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 6999.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 6999.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 6999.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 6999.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 6999.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6999.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6999.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 6999.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 6999.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6999.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6999.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 6999.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 6999.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 6999.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 6999.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 6999.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 6999.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6999.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6999.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6999.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6999.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6999.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6999.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6999.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6999.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6999.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6999.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6999.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6999.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6999.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 6999.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 6999.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 6999.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 6999.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7000.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7000.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7000.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7000.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7000.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7000.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7000.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7000.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7000.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7000.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7000.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7000.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7000.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7000.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7000.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7000.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7000.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7000.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7000.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7000.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7000.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7000.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7000.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7000.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7000.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7000.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7000.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7000.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7000.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7000.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7000.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7000.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7000.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7000.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7000.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7000.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7000.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7000.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7000.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7000.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7000.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7000.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7000.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7000.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7000.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7000.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7000.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7000.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7001.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7001.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7001.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7001.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7001.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7001.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7001.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7001.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7001.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7001.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7001.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7001.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7001.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7001.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7001.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7001.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7001.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7001.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7001.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7001.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7001.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7001.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7001.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7001.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7001.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7001.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7001.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7001.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7001.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7001.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7001.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7001.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7001.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7001.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7001.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7001.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7001.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7001.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7001.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7001.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7001.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7001.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7001.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7001.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7001.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7001.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7001.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7001.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7002.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7002.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7002.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7002.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7002.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7002.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7002.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7002.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7002.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7002.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7002.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7002.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7002.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7002.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7002.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7002.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7002.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7002.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7002.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7002.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7002.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7002.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7002.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7002.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7002.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7002.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7002.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7002.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7002.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7002.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7002.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7002.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7002.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7002.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7002.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7002.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7002.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7002.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7002.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7002.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7002.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7002.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7002.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7002.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7002.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7002.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7002.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7002.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7003.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7003.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7003.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7003.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7003.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7003.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7003.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7003.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7003.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7003.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7003.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7003.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7003.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7003.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7003.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7003.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7003.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7003.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7003.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7003.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7003.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7003.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7003.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7003.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7003.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7003.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7003.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7003.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7003.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7003.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7003.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7003.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7003.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7003.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7003.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7003.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7003.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7003.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7003.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7003.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7003.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7003.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7003.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7003.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7003.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7003.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7003.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7004.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7004.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7004.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7004.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7004.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7004.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7004.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7004.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7004.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7004.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7004.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7004.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7004.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7004.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7004.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7004.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7004.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7004.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7004.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7004.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7004.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7004.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7004.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7004.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7004.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7004.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7004.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7004.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7004.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7004.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7004.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7004.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7004.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7004.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7004.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7004.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7004.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7004.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7004.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7004.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7004.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7004.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7004.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7004.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7004.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7004.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7004.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7005.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7005.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7005.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7005.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7005.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7005.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7005.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7005.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7005.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7005.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7005.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7005.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7005.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7005.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7005.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7005.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7005.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7005.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7005.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7005.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7005.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7005.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7005.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7005.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7005.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7005.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7005.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7005.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7005.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7005.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7005.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7005.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7005.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7005.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7005.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7005.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7005.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7005.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7005.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7005.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7005.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7005.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7005.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7005.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7005.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7005.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7005.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7005.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7006.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7006.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7006.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7006.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7006.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7006.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7006.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7006.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7006.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7006.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7006.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7006.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7006.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7006.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7006.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7006.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7006.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7006.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7006.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7006.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7006.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7006.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7006.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7006.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7006.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7006.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7006.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7006.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7006.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7006.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7006.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7006.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7006.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7006.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7006.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7006.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7006.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7006.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7006.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7006.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7006.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7006.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7006.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7006.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7006.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7006.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7006.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7006.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7006.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7007.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7007.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7007.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7007.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7007.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7007.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7007.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7007.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7007.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7007.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7007.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7007.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7007.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7007.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7007.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7007.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7007.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7007.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7007.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7007.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7007.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7007.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7007.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7007.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7007.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7007.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7007.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7007.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7007.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7007.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7007.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7007.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7007.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7007.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7007.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7007.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7007.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7007.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7007.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7007.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7007.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7007.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7007.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7007.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7007.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7007.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7007.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7007.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7008.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7008.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7008.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7008.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7008.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7008.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7008.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7008.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7008.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7008.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7008.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7008.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7008.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7008.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7008.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7008.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7008.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7008.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7008.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7008.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7008.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7008.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7008.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7008.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7008.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7008.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7008.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7008.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7008.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7008.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7008.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7008.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7008.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7009.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7009.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7009.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7009.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7009.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7009.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7009.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7009.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7009.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7009.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7009.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7009.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7009.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7009.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7009.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7009.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7009.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7009.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7009.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7009.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7009.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7009.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7009.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7009.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7009.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7009.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7009.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7009.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7009.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7009.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7009.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7009.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7009.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7009.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7009.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7009.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7009.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7009.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7009.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7009.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7009.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7009.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7009.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7009.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7009.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7009.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7009.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7009.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7010.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7010.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7010.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7010.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7010.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7010.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7010.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7010.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7010.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7010.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7010.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7010.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7010.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7010.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7010.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7010.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7010.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7010.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7010.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7010.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7010.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7010.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7010.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7010.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7010.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7010.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7010.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7010.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7010.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7010.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7010.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7010.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7010.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7010.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7010.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7010.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7010.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7010.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7010.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7010.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7010.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7010.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7010.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7010.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7010.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7010.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7010.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7010.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7011.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7011.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7011.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7011.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7011.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7011.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7011.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7011.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7011.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7011.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7011.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7011.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7011.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7011.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7011.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7011.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7011.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7011.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7011.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7011.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7011.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7011.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7011.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7011.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7011.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7011.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7011.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7011.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7011.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7011.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7011.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7011.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7011.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7011.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7011.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7011.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7011.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7011.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7011.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7011.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7011.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7011.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7011.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7011.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7011.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7011.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7011.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7011.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7012.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7012.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7012.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7012.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7012.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7012.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7012.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7012.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7012.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7012.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7012.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7012.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7012.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7012.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7012.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7012.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7012.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7012.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7012.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7012.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7012.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7012.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7012.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7012.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7012.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7012.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7012.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7012.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7012.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7012.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7012.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7012.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7012.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7012.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7012.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7012.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7012.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7012.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7012.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7012.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7012.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7012.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7012.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7012.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7012.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7012.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7012.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7012.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7013.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7013.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7013.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7013.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7013.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7013.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7013.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7013.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7013.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7013.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7013.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7013.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7013.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7013.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7013.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7013.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7013.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7013.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7013.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7013.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7013.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7013.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7013.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7013.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7013.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7013.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7013.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7013.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7013.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7013.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7013.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7013.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7013.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7013.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7013.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7013.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7013.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7013.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7013.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7013.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7013.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7013.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7013.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7013.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7013.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7013.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7013.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7013.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7014.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7014.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7014.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7014.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7014.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7014.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7014.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7014.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7014.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7014.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7014.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7014.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7014.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7014.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7014.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7014.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7014.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7014.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7014.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7014.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7014.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7014.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7014.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7014.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7014.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7014.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7014.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7014.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7014.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7014.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7014.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7014.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7014.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7014.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7014.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7014.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7014.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7014.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7014.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7014.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7014.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7014.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7014.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7014.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7014.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7014.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7014.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7014.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7015.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7015.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7015.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7015.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7015.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7015.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7015.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7015.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7015.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7015.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7015.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7015.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7015.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7015.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7015.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7015.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7015.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7015.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7015.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7015.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7015.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7015.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7015.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7015.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7015.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7015.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7015.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7015.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7015.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7015.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7015.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7015.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7015.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7015.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7015.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7015.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7015.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7015.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7015.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7015.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7015.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7015.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7015.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7015.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7015.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7015.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7015.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7015.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7016.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7016.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7016.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7016.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7016.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7016.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7016.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7016.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7016.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7016.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7016.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7016.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7016.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7016.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7016.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7016.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7016.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7016.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7016.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7016.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7016.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7016.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7016.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7016.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7016.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7016.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7016.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7016.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7016.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7016.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7016.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7016.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7016.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7016.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7016.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7016.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7016.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7016.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7016.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7016.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7016.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7016.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7016.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7016.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7016.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7016.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7016.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7017.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7017.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7017.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7017.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7017.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7017.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7017.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7017.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7017.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7017.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7017.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7017.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7017.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7017.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7017.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7017.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7017.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7017.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7017.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7017.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7017.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7017.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7017.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7017.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7017.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7017.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7017.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7017.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7017.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7017.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7017.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7017.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7017.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7017.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7017.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7017.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7017.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7017.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7017.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7017.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7017.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7017.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7017.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7017.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7017.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7017.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7017.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7018.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7018.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7018.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7018.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7018.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7018.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7018.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7018.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7018.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7018.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7018.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7018.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7018.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7018.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7018.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7018.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7018.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7018.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7018.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7018.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7018.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7018.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7018.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7018.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7018.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7018.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7018.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7018.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7018.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7018.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7018.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7018.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7018.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7018.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7018.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7018.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7018.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7018.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7018.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7018.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7018.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7018.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7018.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7018.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7018.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7018.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7018.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7018.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7019.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7019.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7019.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7019.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7019.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7019.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7019.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7019.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7019.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7019.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7019.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7019.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7019.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7019.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7019.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7019.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7019.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7019.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7019.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7019.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7019.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7019.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7019.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7019.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7019.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7019.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7019.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7019.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7019.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7019.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7019.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7019.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7019.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7019.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7019.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7019.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7019.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7019.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7019.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7019.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7019.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7019.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7019.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7019.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7019.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7019.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7019.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7019.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7020.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7020.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7020.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7020.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7020.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7020.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7020.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7020.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7020.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7020.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7020.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7020.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7020.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7020.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7020.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7020.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7020.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7020.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7020.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7020.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7020.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7020.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7020.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7020.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7020.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7020.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7020.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7020.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7020.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7020.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7020.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7020.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7020.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7020.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7020.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7020.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7020.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7020.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7020.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7020.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7020.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7020.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7020.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7020.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7020.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7020.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7020.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7020.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7021.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7021.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7021.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7021.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7021.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7021.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7021.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7021.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7021.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7021.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7021.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7021.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7021.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7021.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7021.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7021.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7021.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7021.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7021.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7021.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7021.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7021.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7021.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7021.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7021.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7021.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7021.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7021.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7021.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7021.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7021.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7021.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7021.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7021.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7021.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7021.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7021.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7021.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7021.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7021.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7021.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7021.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7021.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7021.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7021.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7021.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7021.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7021.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7022.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7022.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7022.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7022.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7022.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7022.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7022.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7022.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7022.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7022.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7022.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7022.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7022.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7022.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7022.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7022.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7022.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7022.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7022.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7022.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7022.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7022.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7022.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7022.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7022.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7022.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7022.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7022.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7022.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7022.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7022.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7022.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7022.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7022.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7022.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7022.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7022.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7022.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7022.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7022.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7022.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7022.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7022.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7022.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7022.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7022.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7022.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7022.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7022.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7022.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7023.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7023.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7023.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7023.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7023.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7023.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7023.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7023.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7023.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7023.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7023.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7023.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7023.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7023.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7023.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7023.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7023.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7023.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7023.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7023.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7023.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7023.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7023.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7023.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7023.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7023.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7023.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7023.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7023.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7023.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7023.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7023.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7023.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7023.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7023.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7023.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7023.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7023.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7023.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7023.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7023.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7023.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7023.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7023.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7023.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7023.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7023.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7024.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7024.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7024.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7024.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7024.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7024.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7024.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7024.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7024.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7024.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7024.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7024.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7024.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7024.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7024.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7024.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7024.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7024.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7024.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7024.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7024.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7024.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7024.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7024.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7024.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7024.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7024.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7024.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7024.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7024.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7024.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7024.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7024.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7024.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7024.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7024.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7024.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7024.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7024.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7024.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7024.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7024.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7024.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7024.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7024.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7024.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7024.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7024.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7025.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7025.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7025.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7025.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7026.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7026.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7026.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7026.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7026.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7026.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7026.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7026.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7026.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7026.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7026.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7026.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7026.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7026.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7026.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7026.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7026.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7026.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7026.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7026.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7026.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7026.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7026.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7026.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7026.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7026.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7026.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7026.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7026.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7026.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7026.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7026.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7026.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7026.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7026.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7026.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7026.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7026.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7026.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7026.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7026.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7026.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7026.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7026.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7026.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7026.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7026.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7026.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7027.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7027.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7027.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7027.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7027.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7027.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7027.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7027.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7027.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7027.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7027.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7027.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7027.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7027.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7027.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7027.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7027.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7027.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7027.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7027.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7027.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7027.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7027.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7027.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7027.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7027.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7027.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7027.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7027.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7027.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7027.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7027.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7027.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7027.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7027.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7027.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7027.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7027.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7027.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7027.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7027.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7027.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7027.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7027.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7027.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7027.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7027.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7027.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7028.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7028.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7028.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7028.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7029.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7029.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7029.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7029.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7029.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7029.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7029.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7029.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7029.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7029.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7029.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7029.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7029.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7029.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7029.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7029.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7029.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7029.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7029.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7029.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7029.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7029.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7029.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7029.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7029.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7029.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7029.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7029.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7029.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7029.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7029.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7029.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7029.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7029.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7029.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7029.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7029.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7029.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7029.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7029.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7029.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7029.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7029.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7029.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7029.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7029.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7029.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7029.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7030.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7030.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7030.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7030.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7030.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7030.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7030.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7030.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7030.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7030.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7030.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7030.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7030.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7030.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7030.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7030.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7030.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7030.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7030.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7030.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7030.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7030.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7030.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7030.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7030.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7030.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7030.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7030.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7030.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7030.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7030.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7030.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7030.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7030.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7030.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7030.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7030.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7030.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7030.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7030.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7030.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7030.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7030.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7030.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7030.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7030.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7030.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7030.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7031.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7031.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7031.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7031.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7031.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7031.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7031.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7031.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7031.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7031.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7031.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7031.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7031.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7031.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7031.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7031.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7031.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7031.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7031.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7031.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7031.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7031.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7031.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7031.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7031.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7031.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7031.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7031.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7031.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7031.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7031.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7031.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7031.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7031.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7031.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7031.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7031.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7031.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7031.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7031.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7031.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7031.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7031.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7031.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7031.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7031.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7031.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7031.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7032.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7032.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7032.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7032.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7033.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7033.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7033.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7033.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7033.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7033.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7033.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7033.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7033.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7033.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7033.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7033.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7033.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7033.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7033.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7033.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7033.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7033.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7033.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7033.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7033.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7033.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7033.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7033.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7033.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7033.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7033.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7033.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7033.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7033.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7033.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7033.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7033.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7033.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7033.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7033.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7033.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7033.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7033.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7033.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7033.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7033.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7033.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7033.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7033.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7033.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7033.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7034.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7034.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7034.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7034.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7034.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7034.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7034.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7034.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7034.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7034.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7034.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7034.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7034.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7034.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7034.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7034.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7034.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7034.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7034.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7034.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7034.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7034.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7034.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7034.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7034.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7034.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7034.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7034.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7034.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7034.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7034.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7034.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7034.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7034.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7034.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7034.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7034.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7034.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7034.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7034.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7034.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7034.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7034.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7034.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7034.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7034.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7034.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7035.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7035.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7035.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7035.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7035.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7035.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7035.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7035.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7035.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7035.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7035.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7035.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7035.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7035.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7035.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7035.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7035.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7035.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7035.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7035.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7035.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7035.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7035.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7035.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7035.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7035.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7035.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7035.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7035.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7035.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7035.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7035.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7035.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7035.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7035.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7035.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7035.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7035.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7035.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7035.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7035.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7035.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7035.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7035.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7035.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7035.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7035.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7035.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7036.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7036.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7036.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7036.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7036.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7036.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7036.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7036.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7036.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7036.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7036.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7036.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7036.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7036.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7036.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7036.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7036.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7036.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7036.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7036.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7036.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7036.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7036.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7036.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7036.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7036.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7036.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7036.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7036.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7036.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7036.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7036.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7036.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7036.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7036.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7036.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7036.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7036.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7036.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7036.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7036.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7036.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7036.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7036.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7036.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7036.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7037.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7037.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7037.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7037.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7037.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7037.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7037.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7037.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7037.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7037.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7037.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7037.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7037.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7037.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7037.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7037.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7037.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7037.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7037.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7037.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7037.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7037.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7037.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7037.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7037.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7037.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7037.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7037.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7037.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7037.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7037.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7037.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7037.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7037.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7037.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7037.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7037.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7037.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7037.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7037.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7037.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7037.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7037.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7037.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7037.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7037.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7037.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7037.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7037.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7038.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7038.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7038.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7038.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7038.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7038.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7038.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7038.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7039.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7039.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7039.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7039.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7039.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7039.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7039.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7039.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7039.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7039.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7039.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7039.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7039.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7039.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7039.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7039.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7039.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7039.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7039.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7039.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7039.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7039.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7039.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7039.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7039.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7039.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7039.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7039.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7039.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7039.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7039.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7039.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7039.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7039.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7039.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7039.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7039.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7039.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7039.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7039.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7039.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7039.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7039.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7039.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7039.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7039.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7039.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7039.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7039.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7040.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7040.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7040.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7040.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7040.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7040.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7040.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7040.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7040.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7040.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7040.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7040.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7040.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7040.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7040.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7040.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7040.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7040.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7040.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7040.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7040.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7040.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7040.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7040.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7040.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7040.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7040.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7040.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7040.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7040.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7040.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7040.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7040.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7040.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7040.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7040.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7040.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7040.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7040.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7040.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7040.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7040.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7040.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7040.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7040.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7040.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7040.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7040.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7040.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7041.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7041.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7041.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7041.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7041.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7041.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7041.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7041.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7041.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7041.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7041.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7041.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7041.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7041.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7041.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7041.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7041.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7041.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7041.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7041.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7041.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7041.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7041.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7041.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7041.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7041.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7041.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7041.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7041.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7041.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7041.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7041.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7041.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7041.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7041.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7041.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7041.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7041.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7041.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7041.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7041.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7041.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7041.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7041.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7041.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7041.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7041.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7041.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7042.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7042.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7042.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7042.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7042.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7042.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7042.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7042.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7042.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7042.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7042.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7042.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7042.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7042.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7042.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7042.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7042.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7042.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7042.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7042.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7042.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7042.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7042.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7042.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7042.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7042.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7042.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7042.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7042.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7042.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7042.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7042.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7042.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7042.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7042.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7042.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7042.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7042.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7042.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7042.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7042.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7042.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7042.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7042.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7042.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7042.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7042.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7042.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7042.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7043.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7043.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7043.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7043.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7043.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7043.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7043.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7043.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7043.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7043.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7043.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7043.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7043.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7043.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7043.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7043.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7043.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7043.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7043.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7043.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7043.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7043.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7043.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7043.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7043.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7043.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7043.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7043.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7043.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7043.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7043.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7043.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7043.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7043.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7043.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7043.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7043.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7043.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7043.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7043.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7043.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7043.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7043.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7043.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7043.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7043.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7043.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7043.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7044.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7044.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7044.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7044.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7044.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7044.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7044.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7044.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7044.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7044.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7044.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7044.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7044.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7044.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7044.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7044.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7044.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7044.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7044.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7044.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7044.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7044.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7044.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7044.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7044.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7044.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7044.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7044.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7044.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7044.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7044.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7044.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7044.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7044.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7044.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7044.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7044.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7044.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7044.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7044.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7044.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7044.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7044.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7044.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7044.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7044.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7044.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7044.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7045.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7045.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7045.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7045.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7045.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7045.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7045.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7045.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7045.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7045.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7045.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7045.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7045.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7045.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7045.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7045.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7045.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7045.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7045.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7045.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7045.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7045.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7045.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7045.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7045.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7045.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7045.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7045.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7045.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7045.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7045.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7045.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7045.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7045.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7045.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7045.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7045.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7045.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7045.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7045.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7045.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7045.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7045.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7045.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7045.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7045.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7045.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7045.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7046.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7046.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7046.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7046.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7046.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7046.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7046.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7046.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7046.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7046.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7046.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7046.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7046.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7046.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7046.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7046.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7046.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7046.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7046.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7046.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7046.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7046.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7046.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7046.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7046.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7046.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7046.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7046.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7046.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7046.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7046.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7047.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7047.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7047.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7047.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7047.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7047.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7047.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7047.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7047.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7047.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7047.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7047.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7047.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7047.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7047.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7047.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7047.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7047.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7047.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7047.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7047.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7047.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7047.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7047.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7047.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7047.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7047.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7047.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7047.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7047.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7047.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7047.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7047.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7047.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7047.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7047.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7047.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7047.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7047.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7047.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7047.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7047.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7047.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7047.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7047.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7047.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7047.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7047.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7048.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7048.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7048.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7048.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7048.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7048.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7048.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7048.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7048.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7048.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7048.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7048.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7048.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7048.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7048.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7048.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7048.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7048.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7048.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7048.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7048.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7048.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7048.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7048.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7048.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7048.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7048.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7048.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7048.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7048.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7048.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7048.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7048.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7048.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7048.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7048.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7048.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7048.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7048.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7048.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7049.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7049.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7049.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7049.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7049.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7049.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7049.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7049.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7049.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7049.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7049.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7049.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7049.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7049.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7049.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7049.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7049.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7049.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7049.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7049.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7049.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7049.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7049.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7049.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7049.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7049.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7049.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7049.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7049.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7049.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7049.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7049.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7049.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7049.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7049.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7049.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7049.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7049.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7049.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7049.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7049.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7049.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7049.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7049.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7049.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7049.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7049.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7049.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7050.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7050.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7050.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7050.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7051.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7051.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7051.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7051.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7051.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7051.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7051.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7051.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7051.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7051.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7051.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7051.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7051.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7051.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7051.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7051.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7051.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7051.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7051.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7051.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7051.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7051.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7051.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7051.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7051.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7051.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7051.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7051.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7051.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7051.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7051.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7051.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7051.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7051.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7051.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7051.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7051.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7051.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7051.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7051.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7051.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7051.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7051.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7051.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7051.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7051.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7051.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7051.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7052.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7052.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7052.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7052.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7052.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7052.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7052.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7052.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7052.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7052.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7052.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7052.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7052.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7052.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7052.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7052.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7052.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7052.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7052.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7052.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7052.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7052.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7052.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7052.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7052.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7052.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7052.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7052.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7052.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7052.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7052.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7052.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7052.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7052.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7052.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7052.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7052.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7052.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7052.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7052.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7052.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7052.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7052.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7052.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7052.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7052.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7052.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7052.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7053.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7053.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7053.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7053.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7053.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7053.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7053.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7053.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7053.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7053.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7053.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7053.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7053.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7053.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7053.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7053.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7053.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7053.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7053.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7053.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7053.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7053.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7053.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7053.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7053.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7053.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7053.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7053.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7053.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7053.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7053.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7053.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7053.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7053.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7053.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7053.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7053.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7053.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7053.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7053.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7053.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7053.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7053.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7053.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7053.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7053.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7053.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7053.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7054.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7054.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7054.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7054.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7054.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7054.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7054.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7054.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7054.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7054.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7054.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7054.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7054.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7054.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7054.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7054.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7054.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7054.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7054.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7054.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7054.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7054.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7054.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7054.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7054.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7054.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7054.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7054.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7054.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7054.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7054.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7054.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7054.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7054.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7054.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7054.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7054.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7054.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7054.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7054.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7054.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7054.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7054.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7054.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7054.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7054.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7054.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7054.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7055.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7055.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7055.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7055.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7055.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7055.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7055.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7055.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7055.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7055.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7055.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7055.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7055.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7055.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7055.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7055.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7055.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7055.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7055.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7055.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7055.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7055.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7055.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7055.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7055.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7055.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7055.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7055.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7055.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7055.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7055.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7055.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7055.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7055.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7055.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7055.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7055.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7055.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7055.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7055.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7055.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7055.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7055.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7055.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7055.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7055.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7055.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7055.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7055.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7056.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7056.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7056.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7056.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7056.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7056.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7056.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7056.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7056.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7056.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7056.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7056.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7056.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7056.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7056.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7056.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7056.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7056.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7056.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7056.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7056.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7056.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7056.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7056.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7056.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7056.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7056.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7056.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7056.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7056.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7056.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7056.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7056.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7056.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7056.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7056.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7056.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7056.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7056.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7056.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7056.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7056.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7056.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7056.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7056.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7056.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7056.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7056.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7057.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7057.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7057.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7057.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7057.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7057.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7057.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7057.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7057.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7057.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7057.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7057.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7057.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7057.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7057.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7057.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7057.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7057.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7057.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7057.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7057.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7057.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7057.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7057.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7057.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7057.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7057.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7057.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7057.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7057.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7057.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7057.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7057.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7057.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7057.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7057.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7057.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7057.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7057.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7057.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7057.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7057.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7057.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7057.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7057.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7057.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7057.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7058.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7058.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7058.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7058.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7058.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7058.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7058.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7058.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7058.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7058.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7058.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7058.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7058.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7058.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7058.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7058.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7058.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7058.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7058.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7058.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7058.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7058.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7058.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7058.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7058.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7058.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7058.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7058.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7058.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7058.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7058.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7058.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7058.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7058.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7058.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7058.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7058.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7058.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7058.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7058.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7058.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7058.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7058.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7058.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7058.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7058.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7058.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7058.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7059.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7059.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7059.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7059.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7059.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7059.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7059.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7059.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7059.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7059.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7059.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7059.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7059.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7059.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7059.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7059.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7059.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7059.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7059.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7059.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7059.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7059.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7059.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7059.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7059.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7059.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7059.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7059.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7059.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7059.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7059.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7059.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7059.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7059.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7059.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7059.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7059.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7059.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7059.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7059.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7059.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7059.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7059.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7059.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7059.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7059.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7059.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7059.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7059.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7060.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7060.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7060.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7060.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7060.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7060.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7060.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7060.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7060.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7060.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7060.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7060.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7060.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7060.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7060.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7060.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7060.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7060.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7060.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7060.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7060.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7060.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7060.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7060.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7060.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7060.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7060.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7060.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7060.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7060.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7060.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7060.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7060.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7060.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7060.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7060.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7060.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7060.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7060.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7060.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7060.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7060.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7060.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7060.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7060.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7060.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7060.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7060.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7061.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7061.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7061.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7061.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7061.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7061.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7061.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7061.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7061.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7061.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7061.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7061.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7061.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7061.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7061.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7061.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7061.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7061.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7061.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7061.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7061.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7061.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7061.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7061.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7061.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7061.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7061.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7061.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7061.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7061.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7061.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7062.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7062.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7062.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7062.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7062.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7062.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7062.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7062.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7062.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7062.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7062.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7062.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7062.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7062.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7062.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7062.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7062.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7062.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7062.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7062.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7062.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7062.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7062.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7062.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7062.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7062.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7062.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7062.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7062.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7062.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7062.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7062.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7062.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7062.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7062.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7062.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7062.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7062.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7062.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7062.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7062.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7062.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7062.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7062.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7062.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7062.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7062.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7062.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7063.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7063.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7063.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7063.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7063.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7063.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7063.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7063.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7063.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7063.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7063.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7063.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7063.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7063.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7063.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7063.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7063.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7063.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7063.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7063.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7063.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7063.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7063.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7063.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7063.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7063.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7063.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7063.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7063.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7063.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7063.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7063.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7063.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7063.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7063.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7063.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7063.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7063.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7063.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7063.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7063.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7063.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7063.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7063.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7063.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7063.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7063.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7063.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7064.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7064.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7064.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7064.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7064.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7064.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7064.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7064.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7064.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7064.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7064.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7064.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7064.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7064.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7065.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7065.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7065.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7065.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7065.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7065.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7065.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7065.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7065.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7065.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7065.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7065.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7065.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7065.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7065.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7065.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7065.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7065.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7065.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7065.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7065.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7065.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7065.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7065.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7065.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7065.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7065.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7065.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7065.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7065.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7065.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7065.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7065.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7065.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7065.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7065.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7065.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7065.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7065.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7065.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7065.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7065.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7065.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7065.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7065.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7065.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7065.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7065.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7066.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7066.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7066.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7066.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7066.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7066.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7066.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7066.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7066.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7066.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7066.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7066.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7066.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7066.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7066.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7066.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7066.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7066.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7066.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7066.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7066.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7066.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7066.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7066.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7066.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7066.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7066.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7066.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7066.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7066.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7066.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7066.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7066.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7066.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7066.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7066.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7066.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7066.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7066.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7066.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7066.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7066.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7066.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7066.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7066.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7066.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7066.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7067.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7067.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7067.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7067.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7067.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7067.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7067.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7067.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7067.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7067.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7067.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7067.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7067.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7067.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7067.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7067.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7067.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7067.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7067.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7067.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7067.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7067.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7067.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7067.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7067.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7067.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7067.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7067.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7067.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7067.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7067.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7067.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7067.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7067.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7067.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7067.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7067.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7067.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7067.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7067.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7067.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7067.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7067.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7067.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7067.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7067.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7067.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7068.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7068.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7068.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7068.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7068.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7068.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7068.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7068.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7068.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7068.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7068.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7068.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7068.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7068.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7068.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7068.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7068.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7068.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7068.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7068.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7068.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7068.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7068.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7068.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7068.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7068.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7068.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7068.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7068.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7068.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7068.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7068.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7068.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7068.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7068.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7068.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7068.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7068.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7068.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7068.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7068.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7068.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7068.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7068.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7068.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7068.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7068.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7068.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7069.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7069.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7069.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7069.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7069.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7069.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7069.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7069.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7069.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7069.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7069.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7069.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7069.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7069.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7069.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7069.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7069.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7069.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7069.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7069.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7069.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7069.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7069.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7069.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7069.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7069.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7070.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7070.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7070.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7070.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7070.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7070.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7070.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7070.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7070.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7070.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7070.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7070.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7070.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7070.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7070.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7070.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7070.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7070.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7070.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7070.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7070.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7070.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7070.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7070.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7070.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7070.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7070.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7070.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7070.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7070.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7070.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7070.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7071.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7071.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7071.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7071.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7071.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7071.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7071.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7071.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7071.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7071.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7071.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7071.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7071.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7071.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7071.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7071.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7071.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7071.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7071.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7071.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7071.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7071.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7071.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7071.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7071.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7071.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7071.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7071.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7071.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7071.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7071.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7071.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7071.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7071.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7071.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7071.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7071.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7071.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7071.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7071.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7071.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7071.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7071.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7071.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7071.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7071.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7071.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7071.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7072.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7072.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7072.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7072.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7072.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7072.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7072.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7072.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7072.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7072.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7072.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7072.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7072.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7072.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7072.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7072.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7072.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7072.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7072.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7072.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7072.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7072.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7072.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7072.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7072.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7072.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7072.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7072.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7072.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7072.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7072.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7072.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7072.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7072.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7072.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7072.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7072.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7072.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7072.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7072.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7073.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7073.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7073.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7073.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7073.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7073.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7073.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7073.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7073.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7073.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7073.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7073.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7073.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7073.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7073.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7073.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7073.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7073.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7073.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7073.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7073.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7073.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7073.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7073.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7073.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7073.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7073.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7073.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7073.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7073.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7073.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7073.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7073.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7073.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7073.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7073.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7073.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7073.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7073.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7073.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7073.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7073.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7073.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7073.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7073.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7073.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7073.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7073.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7074.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7074.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7074.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7074.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7074.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7074.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7074.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7074.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7074.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7074.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7074.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7074.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7074.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7074.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7074.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7074.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7074.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7074.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7074.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7074.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7074.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7074.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7074.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7074.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7074.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7074.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7074.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7074.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7074.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7074.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7074.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7074.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7074.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7074.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7074.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7074.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7074.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7074.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7074.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7074.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7074.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7074.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7074.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7074.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7074.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7074.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7074.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7074.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7074.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7075.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7075.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7075.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7075.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7075.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7075.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7075.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7075.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7075.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7075.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7075.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7075.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7075.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7075.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7075.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7075.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7075.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7075.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7075.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7075.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7075.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7075.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7075.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7075.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7075.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7075.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7075.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7075.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7075.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7075.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7075.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7075.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7075.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7075.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7075.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7075.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7075.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7075.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7075.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7075.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7075.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7075.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7075.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7075.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7075.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7075.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7075.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7075.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7076.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7076.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7076.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7076.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7076.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7076.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7076.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7076.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7076.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7076.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7076.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7076.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7076.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7076.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7076.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7076.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7076.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7076.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7076.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7076.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7076.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7076.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7076.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7076.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7076.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7076.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7076.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7076.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7077.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7077.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7077.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7077.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7077.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7077.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7077.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7077.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7077.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7077.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7077.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7077.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7077.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7077.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7077.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7077.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7077.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7077.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7077.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7077.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7077.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7077.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7077.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7077.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7077.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7077.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7077.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7077.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7077.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7077.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7077.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7077.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7077.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7077.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7077.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7077.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7077.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7077.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7077.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7077.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7077.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7077.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7077.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7077.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7077.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7077.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7077.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7078.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7078.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7078.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7078.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7078.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7078.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7078.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7078.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7078.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7078.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7078.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7078.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7078.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7078.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7078.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7078.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7078.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7078.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7078.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7078.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7078.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7078.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7078.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7078.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7078.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7078.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7078.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7078.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7078.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7078.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7078.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7078.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7078.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7078.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7078.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7078.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7078.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7078.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7078.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7078.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7078.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7078.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7078.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7078.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7078.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7078.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7078.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7078.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7079.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7079.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7079.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7079.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7079.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7079.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7079.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7079.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7079.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7079.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7079.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7079.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7079.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7079.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7079.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7079.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7079.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7079.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7079.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7079.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7079.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7079.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7079.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7079.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7079.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7079.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7079.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7079.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7079.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7079.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7079.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7079.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7079.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7079.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7079.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7079.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7079.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7079.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7079.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7079.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7079.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7079.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7079.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7079.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7079.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7079.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7079.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7079.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7080.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7080.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7080.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7080.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7080.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7080.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7080.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7080.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7080.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7080.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7080.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7080.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7080.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7080.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7080.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7080.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7080.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7080.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7080.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7080.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7080.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7080.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7080.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7080.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7080.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7080.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7080.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7080.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7080.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7080.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7080.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7080.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7080.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7080.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7080.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7080.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7080.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7080.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7080.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7080.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7080.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7080.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7080.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7080.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7080.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7080.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7080.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7080.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7081.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7081.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7081.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7081.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7081.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7081.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7081.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7081.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7081.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7081.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7081.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7081.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7081.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7081.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7081.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7081.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7081.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7081.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7081.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7081.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7081.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7081.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7081.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7081.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7081.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7081.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7081.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7081.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7081.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7081.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7081.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7081.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7081.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7081.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7081.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7081.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7081.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7081.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7081.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7081.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7081.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7081.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7081.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7081.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7081.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7081.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7081.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7081.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7082.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7082.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7082.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7082.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7082.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7082.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7082.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7082.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7082.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7082.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7082.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7082.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7082.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7082.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7082.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7082.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7082.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7082.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7082.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7082.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7082.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7082.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7082.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7082.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7082.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7082.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7082.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7082.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7082.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7082.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7082.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7082.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7082.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7082.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7082.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7082.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7082.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7082.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7082.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7082.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7082.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7082.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7082.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7082.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7082.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7082.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7082.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7082.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7083.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7083.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7083.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7083.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7083.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7083.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7083.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7083.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7083.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7083.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7083.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7084.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7084.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7084.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7084.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7084.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7084.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7084.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7084.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7084.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7084.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7084.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7084.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7084.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7084.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7084.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7084.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7084.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7084.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7084.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7084.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7084.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7084.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7084.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7084.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7084.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7084.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7084.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7084.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7084.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7084.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7084.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7084.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7084.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7084.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7084.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7084.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7084.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7084.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7084.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7084.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7084.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7084.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7084.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7084.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7084.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7084.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7084.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7084.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7085.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7085.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7085.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7085.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7085.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7085.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7085.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7085.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7085.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7085.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7085.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7085.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7085.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7085.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7085.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7085.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7085.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7085.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7085.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7085.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7085.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7085.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7085.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7085.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7085.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7085.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7085.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7085.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7085.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7085.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7085.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7085.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7085.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7085.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7085.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7085.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7085.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7085.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7085.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7085.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7085.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7085.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7085.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7085.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7085.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7085.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7085.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7085.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7086.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7086.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7086.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89360] >[ 7086.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89360] width 1920 pitch 7680 (/4 1920) >[ 7086.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7086.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7086.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2c2c890] >[ 7086.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2c2c890] width 1920 pitch 7680 (/4 1920) >[ 7086.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2cc2780] >[ 7086.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2cc2780] width 1920 pitch 7680 (/4 1920) >[ 7086.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7086.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7086.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7086.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7086.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45d35b0] >[ 7086.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45d35b0] width 1920 pitch 7680 (/4 1920) >[ 7086.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7086.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7086.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7086.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7086.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7086.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7086.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x465a0d0] >[ 7086.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x465a0d0] width 1920 pitch 7680 (/4 1920) >[ 7086.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582590] >[ 7086.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582590] width 1920 pitch 7680 (/4 1920) >[ 7086.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c0d00] >[ 7086.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c0d00] width 1920 pitch 7680 (/4 1920) >[ 7086.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4134750] >[ 7086.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4134750] width 1920 pitch 7680 (/4 1920) >[ 7086.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f2b70] >[ 7086.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f2b70] width 1920 pitch 7680 (/4 1920) >[ 7086.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49fd950] >[ 7086.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49fd950] width 1920 pitch 7680 (/4 1920) >[ 7086.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7086.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7086.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7086.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7086.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7086.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7086.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7086.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7086.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7086.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 7086.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x438ff00] >[ 7086.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x438ff00] width 1920 pitch 7680 (/4 1920) >[ 7086.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457ce50] >[ 7086.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457ce50] width 1920 pitch 7680 (/4 1920) >[ 9818.881] [mi] EQ overflowing. Additional events will be discarded until existing events are processed. >[ 9819.019] >[ 9819.019] Backtrace: >[ 9821.175] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x4652d6] >[ 9821.176] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x5514db] >[ 9821.176] 2: /usr/bin/Xorg (0x400000+0x47f32) [0x447f32] >[ 9821.223] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7feb309ab000+0x60e4) [0x7feb309b10e4] >[ 9821.223] 4: /usr/bin/Xorg (0x400000+0x807b7) [0x4807b7] >[ 9821.223] 5: /usr/bin/Xorg (0x400000+0xa4ab0) [0x4a4ab0] >[ 9821.223] 6: /lib64/libpthread.so.0 (0x313d600000+0xefe0) [0x313d60efe0] >[ 9821.223] 7: /usr/bin/Xorg (0x400000+0x6aba0) [0x46aba0] >[ 9821.223] 8: /lib64/libpthread.so.0 (0x313d600000+0xefe0) [0x313d60efe0] >[ 9821.223] 9: /usr/lib64/xorg/modules/libfb.so (fbBlt+0xc22) [0x7feb32ce2872] >[ 9821.223] 10: /usr/lib64/xorg/modules/libfb.so (fbBltStip+0x40) [0x7feb32ce2b60] >[ 9821.223] 11: /usr/lib64/xorg/modules/libfb.so (fbPutZImage+0x195) [0x7feb32ce7555] >[ 9821.223] 12: /usr/lib64/xorg/modules/libexa.so (0x7feb32ef5000+0x1052d) [0x7feb32f0552d] >[ 9821.223] 13: /usr/lib64/xorg/modules/libexa.so (0x7feb32ef5000+0x8bfe) [0x7feb32efdbfe] >[ 9821.223] 14: /usr/bin/Xorg (0x400000+0x105482) [0x505482] >[ 9821.223] 15: /usr/bin/Xorg (0x400000+0xd910c) [0x4d910c] >[ 9821.223] 16: /usr/bin/Xorg (0x400000+0xda3c5) [0x4da3c5] >[ 9821.223] 17: /usr/bin/Xorg (0x400000+0x3447a) [0x43447a] >[ 9821.223] 18: /usr/bin/Xorg (0x400000+0x23485) [0x423485] >[ 9821.223] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x313ce21735] >[ 9821.223] 20: /usr/bin/Xorg (0x400000+0x2375d) [0x42375d] >[ 9821.223] >[ 9821.224] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack. >[ 9821.224] [mi] mieq is *NOT* the cause. It is a victim. >[ 9822.416] [mi] Increasing EQ size to 512 to prevent dropped events. >[ 9822.427] [mi] EQ processing has resumed after 73 dropped events. >[ 9822.427] [mi] This may be caused my a misbehaving driver monopolizing the server's resources.
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